Table 2-23 A1425A, A" />
參數(shù)資料
型號： A1415A-1VQG100I
廠商： Microsemi SoC
文件頁數(shù)： 29/90頁
文件大?。?/td> 0K
描述： IC FPGA 1500 GATES 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 3
LAB/CLB數(shù)： 200
輸入/輸出數(shù)： 80
門數(shù)： 1500
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 27
A1425A, A14V25A Timing Characteristics (continued)
Table 2-23 A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
I/O Module Input Propagation Delays
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max.
Min.
Max.
tINY
Input Data Pad to Y
2.8
3.2
3.6
4.2
5.5
ns
tICKY
Input Reg IOCLK Pad to Y
4.7
5.3
6.0
7.0
9.2
ns
tOCKY
Output Reg IOCLK Pad to Y
4.7
5.3
6.0
7.0
9.2
ns
tICLRY Input Asynchronous Clear to Y
4.7
5.3
6.0
7.0
9.2
ns
tOCLRY Output Asynchronous Clear to Y
4.7
5.3
6.0
7.0
9.2
ns
Predicted Input Routing Delays2
tRD1
FO = 1 Routing Delay
0.9
1.0
1.1
1.3
1.7
ns
tRD2
FO = 2 Routing Delay
1.2
1.4
1.6
1.8
2.4
ns
tRD3
FO = 3 Routing Delay
1.4
1.6
1.8
2.1
2.8
ns
tRD4
FO = 4 Routing Delay
1.7
1.9
2.2
2.5
3.3
ns
tRD8
FO = 8 Routing Delay
2.8
3.2
3.6
4.2
5.5
ns
I/O Module Sequential Timing (wrt IOCLK pad)
tINH
Input F-F Data Hold
0.0
ns
tINSU
Input F-F Data Setup
1.8
2.0
2.3
2.7
3.0
ns
tIDEH
Input Data Enable Hold
0.0
ns
tIDESU Input Data Enable Setup
5.8
6.5
7.5
8.6
ns
tOUTH
Output F-F Data hold
0.7
0.8
0.9
1.0
ns
tOUTSU Output F-F Data Setup
0.7
0.8
0.9
1.0
ns
tODEH Output Data Enable Hold
0.3
0.4
0.5
ns
fODESU Output Data Enable Setup
1.3
1.5
1.7
2.0
ns
Notes: *
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
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A1415A-1VQG100M 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 150MHZ 0.8UM 5V 100VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 1500 GATES 100-VQFP MIL 制造商:Microsemi Corporation 功能描述:IC FPGA 80 I/O 100VQFP
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