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參數(shù)資料
| 型號： | A1425A-PQG100I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 310 CLBS, 2500 GATES, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 56/68頁 |
| 文件大?。?/td> | 489K |
| 代理商： | A1425A-PQG100I |
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Hermetic Device Resources
Pin Description
CLKA
Clock A (Input)
Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
CLKB
Clock B (Input)
Clock input for clock distribution networks. The Clock input
is buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired)
Array Clock (Input)
Clock input for sequential modules. This input is directly
wired to each S-Module and offers clock speeds independent
of the number of S-Modules being driven. This pin can also be
used as an I/O.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. Unused I/O pins
are tristated by the Designer Series software.
IOCLK
Dedicated (Hard-wired)
I/O Clock (Input)
Clock input for I/O modules. This input is directly wired to
each I/O module and offers clock speeds independent of the
number of I/O modules being driven. This pin can also be
used as an I/O.
IOPCL
Dedicated (Hard-wired)
I/O Preset/Clear (Input)
Input for I/O preset or clear. This global input is directly
wired to the preset and clear inputs of all I/O registers. This
pin functions as an I/O when no I/O preset or clear macros
are used.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide Actionprobe capability, the
MODE pin should be terminated to GND through a 10K
resistor so that the MODE pin can be pulled high when
required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA
Probe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB
Probe B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial
data
input
for
diagnostic
probe
and
device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
DCLK
Diagnostic Clock (Input)
Clock input for diagnostic probe and device programming.
DCLK is active when the MODE pin is HIGH. This pin
functions as an I/O when the MODE pin is LOW.
VCC
5 V Supply Voltage
HIGH supply voltage.
Device
Series
Logic
Modules
User I/Os
CPGA
CQFP
Gates
100-pin
133-pin
175-pin
207-pin
257-pin
132-pin
196-pin
256-pin
A1415
200
1500
80
—
A1425
310
2500
—
100
—
100
—
A1440
564
4000
—
140
—
A1460
848
6000
—
168
—
168
—
A14100
1377
10000
—
228
—
228
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| A1425A-VQG100C | FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQFP100 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A1425A-PQG160C | 功能描述:IC FPGA 2500 GATES 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| A1425A-PQG160I | 功能描述:IC FPGA 2500 GATES 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| A1425A-STDCQ132B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| A1425A-STDCQ132M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| A1425A-VQ100C | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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