Table 2-33 A1460A, A" />
參數(shù)資料
型號: A1460A-PQG160C
廠商: Microsemi SoC
文件頁數(shù): 40/90頁
文件大小: 0K
描述: IC FPGA 6K GATES 160-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ACT™ 3
LAB/CLB數(shù): 848
輸入/輸出數(shù): 131
門數(shù): 6000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 160-BQFP
供應(yīng)商設(shè)備封裝: 160-PQFP(28x28)
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 - 37
A1460A, A14V60A Timing Characteristics (continued)
Table 2-33 A1460A, A14V60A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
Dedicated (hardwired) I/O Clock Network
–3 Speed1 –2 Speed1 –1 Speed Std. Speed 3.3 V Speed1 Units
Parameter/Description
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max.
tIOCKH
Input Low to High (pad to I/O module
input)
2.3
2.6
3.0
3.5
4.5
ns
tIOPWH
Minimum Pulse Width High
2.4
3.2
3.8
4.8
6.5
ns
tIPOWL
Minimum Pulse Width Low
2.4
3.2
3.8
4.8
6.5
ns
tIOSAPW Minimum Asynchronous Pulse Width
2.4
3.2
3.8
4.8
6.5
ns
tIOCKSW Maximum Skew
0.6
ns
tIOP
Minimum Period
5.0
6.8
8.0
10.0
13.4
ns
fIOMAX
Maximum Frequency
200
150
125
100
75
MHz
Dedicated (hardwired) Array Clock
tHCKH
Input Low to High (pad to S-module
input)
3.7
4.1
4.7
5.5
7.0
ns
tHCKL
Input High to Low (pad to S-module
input)
3.7
4.1
4.7
5.5
7.0
ns
tHPWH
Minimum Pulse Width High
2.4
3.2
3.8
4.8
6.5
ns
tHPWL
Minimum Pulse Width Low
2.4
3.2
3.8
4.8
6.5
ns
tHCKSW
Delta High to Low, Low Slew
0.6
ns
tHP
Minimum Period
5.0
6.8
8.0
10.0
13.4
ns
fHMAX
Maximum Frequency
200
150
125
100
75
MHz
Routed Array Clock Networks
tRCKH
Input Low to High (FO = 64)
6.0
6.8
7.7
9.0
11.8
ns
tRCKL
Input High to Low (FO = 64)
6.0
6.8
7.7
9.0
11.8
ns
tRPWH
Min. Pulse Width High (FO = 64)
4.1
4.5
5.4
6.1
8.2
ns
tRPWL
Min. Pulse Width Low (FO = 64)
4.1
4.5
5.4
6.1
8.2
ns
tRCKSW
Maximum Skew (FO = 128)
1.2
1.4
1.6
1.8
ns
tRP
Minimum Period (FO = 64)
8.3
9.3
11.1
12.5
16.7
ns
fRMAX
Maximum Frequency (FO = 64)
120
105
90
80
60
MHz
Clock-to-Clock Skews
tIOHCKSW I/O Clock to H-Clock Skew
0.0
2.6
0.0
2.7
0.0
2.9
0.0
3.0
0.0
3.0
ns
tIORCKSW I/O Clock to R-Clock Skew (FO = 64)
(FO = 216)
0.0
1.7
5.0
0.0
1.7
5.0
0.0
1.7
5.0
0.0
1.7
5.0
0.0
5.0
ns
tHRCKSW H-Clock to R-Clock Skew (FO = 64)
(FO = 216)
0.0
1.3
3.0
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
0.0
1.0
3.0
ns
Notes:
1. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
2. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
ASC49DRTH-S734 CONN EDGECARD 98POS DIP .100 SLD
A54SX16P-1VQ100M IC FPGA SX 24K GATES 100-VQFP
A54SX16P-1VQG100M IC FPGA SX 24K GATES 100-VQFP
ASC49DREN-S734 CONN EDGECARD 98POS .100 EYELET
M1AFS1500-2FG676I IC FPGA 8MB FLASH 1.5M 676-FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1460A-PQG160I 功能描述:IC FPGA 6K GATES 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
A1460A-PQG208C 功能描述:IC FPGA 6K GATES 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
A1460A-PQG208I 功能描述:IC FPGA 6K GATES 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ACT™ 3 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP,帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP(75x75)
A1460A-STDCQ196B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
A1460A-STDCQ196M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC