參數(shù)資料
型號(hào): A1460A-PQG208I
廠商: Microsemi SoC
文件頁(yè)數(shù): 86/90頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 6K GATES 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: ACT™ 3
LAB/CLB數(shù): 848
輸入/輸出數(shù): 167
門(mén)數(shù): 6000
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
R e visio n 3
4 -1
4 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the datasheet.
Revision
Changes
Page
Revision 3
(January 2012)
The description for SDO pins had earlier been removed from the datasheet and has
now been included again, in the "Pin Descriptions" section (SAR 35820).
SDO pin numbers had earlier been removed from package pin assignment tables in
the datasheet, and have now been restored to the pin tables (SAR 35820).
Revision 2
(September 2011)
The ACT 3 datasheet was formatted newly in the style used for current datasheets.
The same information is present (other than noted in the list of changes for this
revision) but divided into chapters.
N/A
The datasheet was revised to note in multiple places that speed grades –2 and –3
have been discontinued. The following device/package combinations have been
discontinued for all speed grades and temperatures (SAR 33872):
A1415 PG100
A1425 PG133
A1440 PG175
A1460 BG225
I and
others
The "Features" section was revised to state the clock-to-ouput time and on-chip
performance for –1 speed grade as 9.0 ns and 186 MHz. The "General Description"
section was revised in accordance (SAR 33872).
The maximum performance values were updated in Table 1 ACT 3 Family Product
Information, and now reflect worst-case commercial for the –1 speed grade (SAR
33872).
The "Product Plan" table was updated as follows to conform to current offerings (SAR
33872):
The A1415A device is offered in PL84, PG100, and VQ100 packages for Military
application.
The A1440A device is offered in TQ176 and VQ100 packages for Industrial
application.
include data for all speed grades instead of only –3 (SAR 33872).
revised to reflect values for the –1 speed grade (SAR 33872).
Figure 2-10 Timing Model was updated to show data for the –1 speed grade instead
of –3 (SAR 33872).
Conditions was updated to include data for all speed grades instead of only –3 (SAR
33872).
Package names used in the "Package Pin Assignments" section and throughout the
document were revised to match standards given in Package Mechanical Drawings
(SAR 27395).
相關(guān)PDF資料
PDF描述
EP2AGX95EF29C6 IC ARRIA II GX FPGA 95K 780FBGA
EP2AGX65DF29I5 IC ARRIA II GX FPGA 65K 780FBGA
211667-1 CONN D-SUB RCPT HSING 15POS HD
211642-4 CONN D-SUB PLUG 50POS CRIMP
EP1SGX25CF672C6N IC STRATIX GX FPGA 25KLE 672FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1460A-STDCQ196B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
A1460A-STDCQ196M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
A1460ASTDPQ207B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
A1460ASTDPQ207C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
A1460ASTDPQ207M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC