Table 2-22 A1425A, A14V25A Worst-Case Commercial " />
參數(shù)資料
型號(hào)： A14V15A-VQG100C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 28/90頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 1500 GATES 3.3V 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 3
LAB/CLB數(shù)： 200
輸入/輸出數(shù)： 80
門數(shù)： 1500
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Detailed Specifications
2- 26
R e visio n 3
A1425A, A14V25A Timing Characteristics
Table 2-22 A1425A, A14V25A Worst-Case Commercial Conditions, VCC = 4.75 V, TJ = 70°C
1
Logic Module Propagation Delays2
–3 Speed3
–2 Speed3
–1 Speed
Std. Speed
3.3 V Speed1 Units
Parameter/Description
Min.
Max.
Min. Max. Min.
Max.
Min.
Max.
Min.
Max.
tPD
Internal Array Module
2.0
2.3
2.6
3.0
3.9
ns
tCO
Sequential Clock to Q
2.0
2.3
2.6
3.0
3.9
ns
tCLR
Asynchronous Clear to Q
2.0
2.3
2.6
3.0
3.9
ns
Predicted Routing Delays4
tRD1
FO = 1 Routing Delay
0.9
1.0
1.1
1.3
1.7
ns
tRD2
FO = 2 Routing Delay
1.2
1.4
1.6
1.8
2.4
ns
tRD3
FO = 3 Routing Delay
1.4
1.6
1.8
2.1
2.8
ns
tRD4
FO = 4 Routing Delay
1.7
1.9
2.2
2.5
3.3
ns
tRD8
FO = 8 Routing Delay
2.8
3.2
3.6
4.2
5.5
ns
Logic Module Sequential Timing
tSUD
Flip-Flop Data Input Setup
0.5
0.6
0.7
0.8
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tSUD
Latch Data Input Setup
0.5
0.6
0.7
0.8
ns
tHD
Latch Data Input Hold
0.0
ns
tWASYN Asynchronous Pulse Width
1.9
2.4
3.2
3.8
4.8
ns
tWCLKA Flip-Flop Clock Pulse Width
1.9
2.4
3.2
3.8
4.8
ns
tA
Flip-Flop Clock Input Period
4.0
5.0
6.8
8.0
10.0
ns
fMAX
Flip-Flop Clock Frequency
250
200
150
125
100
MHz
Notes:
1. VCC = 3.0 V for 3.3 V specifications.
2. For dual-module macros, use tPD + tRD1 + tPDn + tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
3. The –2 and –3 speed grades have been discontinued. Refer to PDN 0104, PDN 0203, PDN 0604, and PDN 1004 at
4. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case
performance. Post-route timing is based on actual routing delay measurements performed on the device prior to
shipment.
相關(guān)PDF資料
PDF描述
A14V15A-VQ100C IC FPGA 1500 GATES 3.3V 100-VQFP
AX500-FGG676 IC FPGA AXCELERATOR 500K 676FBGA
AX500-FG676 IC FPGA AXCELERATOR 500K 676FBGA
AFS600-FG256I IC FPGA 4MB FLASH 600K 256FBGA
AFS600-FGG256I IC FPGA 4MB FLASH 600K 256FBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A14V25AA-1BG208B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family
A14V25AA-1BG208C 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family
A14V25AA-1BG208I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family
A14V25AA-1BG208M 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family
A14V25AA-1CQ208B 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Accelerator Series FPGAs - ACT 3Family
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*