參數(shù)資料
型號(hào)： A32400DX-1PQ240I
元件分類： FPGA
英文描述： FPGA, 2526 CLBS, 40000 GATES, PQFP240
封裝： PLASTIC, QFP-240
文件頁(yè)數(shù)： 21/22頁(yè)
文件大小： 217K
代理商： A32400DX-1PQ240I
8
allows the designer to probe any internal node during device
operation to aid in debugging a design.
JTAG Boundary Scan Testing (BST)
Device pin spacing is decreasing with the advent of fine-pitch
packages
such
as
TQFP
and
BGA
packages
and
manufacturers are routinely implementing surface-mount
technology with multi-layer PC boards. Boundary scan is
becoming an attractive tool to help systems manufacturers
test their PC boards. The Joint Test Action Group (JTAG)
developed the IEEE Boundary Scan standard 1149.1 to
facilitate board-level testing during manufacturing.
IEEE Standard 1149.1 defines a 4-pin Test Access Port
(TAP) interface for testing integrated circuits in a system.
The 3200DX family provides four JTAG BST pins: Test
Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and
Test Mode Select (TMS). Devices are configured in a JTAG
“chain” where BST data can be transmitted serially between
devices via TDO to TDI interconnections. The TMS and
TCK signals are shared between all devices in the JTAG
chain so that all components operate in the same state.
The 3200DX family implements a subset of the IEEE 1149.1
Boundary Scan Test (BST) instruction in addition to a private
instruction to allow the use of Actel’s Actionprobe facility
with JTAG BST. Refer to the IEEE 1149.1 specification for
detailed information regarding JTAG testing.
JTAG Architecture
The
3200DX’s
JTAG
BST
function
is
enabled
by
programming the JTAG anti-fuse. When JTAG BST is not
enabled, the TMS, TCLK, and TDI pins become user I/O.
Otherwise, these three pins are dedicated exclusively to
JTAG testing.
Figure 9 JTAG BST Circuitry
JPROBE Register
Boundary Scan Register
Instruction
Decode
Control Logic
TAP Controller
Instruction
Register
Bypass
Register
TMS
TCLK
TDI
Output
MUX
TDO
The 3200DX JTAG BST circuitry consist of a Test Access
Port (TAP) controller, JTAG instruction register, JPROBE
register, bypass register and boundary scan register. Figure 9
is a block diagram of the 3200DX JTAG circuitry.
When a device is operating in JTAG BST mode, four I/O pins
are used for the TDI, TDO, TMS, and TCK signals. An active
reset (nTRST) pin is not supported, however the 3200DX
contains power-on reset circuitry which resets the JTAG BST
circuitry upon power-up. The following table summarizes the
functions of the JTAG BST signals.
JTAG BST Instructions
JTAG BST testing within the 3200DX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
JTAG
Signal
Name
Function
TDI
Test Data In
Serial data input for JTAG
instructions and data. Data is
shifted in on the rising edge of
TCLK.
TDO
Test Data Out
Serial data output for JTAG
instructions and test data.
TMS
Test Mode
Select
Serial data input for JTAG test
mode. Data is shifted in on the
rising edge of TCLK.
TCK
Test Clock
Clock signal to shift the JTAG
data into the device.
相關(guān)PDF資料
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A32400DX-2BG313C FPGA, 2526 CLBS, 40000 GATES, PBGA313
A32400DX-2BG313I FPGA, 2526 CLBS, 40000 GATES, PBGA313
A32400DX-2PQ240C FPGA, 2526 CLBS, 40000 GATES, PQFP240
A32400DX-2PQ240I FPGA, 2526 CLBS, 40000 GATES, PQFP240
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A32400DX-1RQ240C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A32400DX-1RQ240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A32400DX-2RQ240C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A32400DX-2RQ240I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A32400DX-3RQ240C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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