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參數(shù)資料
| 型號： | A32400DX-BG313I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 2526 CLBS, 40000 GATES, PBGA313 |
| 封裝： | BGA-313 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 217K |
| 代理商： | A32400DX-BG313I |
7
3200DX Field Programmable Gate Arrays – The System Logic Integrator Family
Clock Networks
Two low-skew, high fanout clock distribution networks are
provided in each 3200DX device. These networks are
referred to as CLK0 and CLK1. Each network has a clock
module (CLKMOD) that selects the source of the clock
signal and may be driven as follows:
1.
Externally from the CLKA pad
2.
Externally from the CLKB pad
3.
Internally from the CLKINA input
4.
Internally from the CLKINB input
The clock modules are located in the top row of I/O modules.
Clock drivers and a dedicated horizontal clock track are
located in each horizontal routing channel.
The user controls the clock module by selecting one of two
clock macros from the macro library. The macro CLKBUF is
used to connect one of the two external clock pins to a clock
network, and the macro CLKINT is used to connect an
internally generated clock signal to a clock network. Since
both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. The clock input pads
may also be used as normal I/Os, bypassing the clock
networks (see Figure 7).
The 3200DX devices which contain SRAM modules (all
except A3265DX and A32140DX) have four additional
register control resources, called Quadrant Clock Networks
(Figure 8). Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its quadrant
of the device. Quadrant clock signals can originate from
specific I/O pins or from the internal array and can be used as
a secondary register clock, register clear, or output enable.
Test Circuitry
The 3200DX provides two modes of device and/or
board-level testing; JTAG 1149.1 Boundary Scan Testing
and Actel’s Actionprobe test facility. Once a 3200DX
device has been programmed, the Actionprobe test facility
Figure 7 Clock Networks
CLKB
CLKA
FROM
PADS
CLOCK
DRIVERS
CLKMOD
CLKINB
CLKINA
S0
S1
INTERNAL
SIGNAL
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
CLOCK TRACKS
Figure 8 Quadrant Clock Network
Quad
Clock
Module
QCLKA
QCLKB
*QCLK1IN
S0 S1
QCLK1
Quad
Clock
Module
*QCLK2IN
S0 S1
QCLK2
Quad
Clock
Module
QCLKC
QCLKD
*QCLK3IN
S0
S1
QCLK3
Quad
Clock
Module
*QCLK4IN
S0
S1
QCLK4
*QCLK1IN, QCLK2IN, QCLK3IN, and QCKL4IN are internally generated signals.
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PDF描述 |
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| A32400DX-PQ240C | FPGA, 2526 CLBS, 40000 GATES, PQFP240 |
| A32400DX-PQ240I | FPGA, 2526 CLBS, 40000 GATES, PQFP240 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A32400DX-FRQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-FRQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-RQ240C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32400DX-RQ240I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| A32401-0009 | 功能描述:重負荷電源連接器 A32 PLUG 1/0 AWG RoHS:否 制造商:Hirose Connector 系列:PS2 產(chǎn)品類型:Connectors 位置/觸點數(shù)量: 端接類型:Crimp 觸點材料: 觸點電鍍:Gold 電壓額定值: 電流額定值:300 A 附件類型: |
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