ProASIC3 Flash Family FPGAs
Revision 13
2-33
Timing Characteristics
Table 2-41 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Advanced I/O Banks
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
4 mA
Std.
0.66
7.66
0.04
1.02
0.43
7.80
6.59
2.65
2.61
10.03
8.82
ns
–1
0.56
6.51
0.04
0.86
0.36
6.63
5.60
2.25
2.22
8.54
7.51
ns
–2
0.49
5.72
0.03
0.76
0.32
5.82
4.92
1.98
1.95
7.49
6.59
ns
6 mA
Std.
0.66
4.91
0.04
1.02
0.43
5.00
4.07
2.99
3.20
7.23
6.31
ns
–1
0.56
4.17
0.04
0.86
0.36
4.25
3.46
2.54
2.73
6.15
5.36
ns
–2
0.49
3.66
0.03
0.76
0.32
3.73
3.04
2.23
2.39
5.40
4.71
ns
8 mA
Std.
0.66
4.91
0.04
1.02
0.43
5.00
4.07
2.99
3.20
7.23
6.31
ns
–1
0.56
4.17
0.04
0.86
0.36
4.25
3.46
2.54
2.73
6.15
5.36
ns
–2
0.49
3.66
0.03
0.76
0.32
3.73
3.04
2.23
2.39
5.40
4.71
ns
12 mA
Std.
0.66
3.53
0.04
1.02
0.43
3.60
2.82
3.21
3.58
5.83
5.06
ns
–1
0.56
3.00
0.04
0.86
0.36
3.06
2.40
2.73
3.05
4.96
4.30
ns
–2
0.49
2.64
0.03
0.76
0.32
2.69
2.11
2.40
2.68
4.36
3.78
ns
16 mA
Std.
0.66
3.33
0.04
0.43
3.39
2.56
3.26
3.68
5.63
4.80
ns
–1
0.56
2.83
0.04
0.86
0.36
2.89
2.18
2.77
3.13
4.79
4.08
ns
–2
0.49
2.49
0.03
0.76
0.32
2.53
1.91
2.44
2.75
4.20
3.58
ns
24 mA
Std.
0.66
3.08
0.04
1.02
0.43
3.13
2.12
3.32
4.06
5.37
4.35
ns
–1
0.56
2.62
0.04
0.86
0.36
2.66
1.80
2.83
3.45
4.57
3.70
ns
–2
0.49
2.30
0.03
0.76
0.32
2.34
1.58
2.48
3.03
4.01
3.25
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.