Global Resources in Actel Low-Power Flash Devices
3- 12
v1.1
The current synthesis tool libraries only infer the CLKBUF or CLKINT macros in the netlist. All other
global macros must be instantiated manually into your HDL code. The following is an example of
CLKBUF_LVCMOS25 global macro instantiations that you can copy and paste into your code:
VHDL
component clkbuf_lvcmos25
port (pad : in std_logic; y : out std_logic);
end component
begin
-- concurrent statements
u2 : clkbuf_lvcmos25 port map (pad =>
ext_clk, y => int_clk);
end
Verilog
module design (______);
input _____;
output ______;
clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk);
endmodule
Using Global Macros in Synplicity
The Synplify synthesis tool automatically inserts global buffers for nets with high fanout during
synthesis. By default, Synplicity puts six global macros (CLKBUF or CLKINT) in the netlist, including
any global instantiation or PLL macro. Synplify always honors your global macro instantiation. If
you have a PLL (only primary output is used) in the design, Synplify adds five more global buffers in
the netlist. Synplify uses the following global counting rule to add global macros in the netlist:
1. CLKBUF: 1 global buffer
2. CLKINT: 1 global buffer
3. CLKDLY: 1 global buffer
4. PLL: 1 to 3 global buffers
–
GLA, GLB, GLC, YB, and YC are counted as 1 buffer.
–
GLB or YB is used or both are counted as 1 buffer.
–
GLC or YC is used or both are counted as 1 buffer.
CLKBUF_GTLP25
GTL+ clock buffer with 2.5 V CMOS voltage level1
CLKBUF_GTLP33
GTL+ clock buffer with 3.3 V CMOS voltage level1
CLKBUF_ HSTL _I
HSTL Class I clock buffer1
CLKBUF_ HSTL _II
HSTL Class II clock buffer1
CLKBUF_SSTL2_I
SSTL2 Class I clock buffer1
CLKBUF_SSTL2_II
SSTL2 Class II clock buffer1
CLKBUF_SSTL3_I
SSTL3 Class I clock buffer1
CLKBUF_SSTL3_II
SSTL3 Class II clock buffer1
Table 3-7
I/O Standards within CLKBUF (continued)
Name
Description
Notes:
1. Supported in only the IGLOOe and ProASIC3E devices
2. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology.