Clock Conditioning Circuits in IGLOO and ProASIC3 Devices
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The CCC block is fully configurable. The following two sources can act as the CCC configuration
bits.
Flash Configuration Bits
The flash configuration bits are the configuration bits associated with programmed flash switches.
These bits are used when the CCC is in static configuration mode. Once the device is programmed,
these bits cannot be modified. They provide the default operating state of the CCC.
Dynamic Shift Register Outputs
This source does not require core reprogramming and allows core-driven dynamic CCC
reconfiguration. When the dynamic register drives the configuration bits, the user-defined core
circuit takes full control over SDIN, SDOUT, SCLK, SSHIFT, and SUPDATE. The configuration bits can
consequently be dynamically changed through shift and update operations in the serial register
interface. Access to the logic core is accomplished via the dynamic bits in the specific tiles assigned
to the PLLs.
Figure 4-17 illustrates a simplified block diagram of the MUX architecture in the CCCs.
The selection between the flash configuration bits and the bits from the configuration register is
made using the MODE signal shown in
Figure 4-17. If the MODE signal is logic HIGH, the dynamic
shift register configuration bits are selected. There are 81 control bits to configure the different
functions of the CCC.
Each group of control bits is assigned a specific location in the configuration shift register. For a list
of the 81 configuration bits (C[80:0]) in the CCC and a description of each, refer to
"PLLwith the new configuration data and programmed into the CCC using the following ports:
SDIN: The configuration bits are serially loaded into a shift register through this port. The
LSB of the configuration data bits should be loaded first.
SDOUT: The shift register contents can be shifted out (LSB first) through this port using the
shift operation.
SCLK: This port should be driven by the shift clock.
SSHIFT: The active-high shift enable signal should drive this port. The configuration data will
be shifted into the shift register if this signal is HIGH. Once SSHIFT goes LOW, the data
shifting will be halted.
SUPDATE: The SUPDATE signal is used to configure the CCC with the new configuration bits
when shifting is complete.
To access the configuration ports of the shift register (SDIN, SDOUT, SSHIFT, etc.), the user should
instantiate the CCC macro in his design with appropriate ports. Actel recommends that users
choose SmartGen to generate the CCC macros with the required ports for dynamic reconfiguration.
Figure 4-17 The CCC Configuration MUX Architecture
SDIN
SCLK
RESET_ENABLE
SDOUT
SSHIFT
MODE
SUPDATE
Configuration Bits
Dynamic Shift
Register
Flash
Programming
Configuration
Bits
<80:0>
<80>
<79:0>