
Low-Power Modes in Actel ProASIC3/E FPGAs
2- 4
v1.1
Table 2-2
Using ULSICC Macro*
VHDL
Verilog
COMPONENT ULSICC
port (
LSICC
: in
STD_ULOGIC);
END COMPONENT;
Example:
COMPONENT ULSICC
port (
LSICC
: in
STD_ULOGIC);
END COMPONENT;
attribute syn_noprune : boolean;
attribute syn_noprune of u1 : label is true;
u1: ULSICC port map(myInputSignal);
module ULSICC(LSICC);
input LSICC;
endmodule
Example:
ULSICC U1(.LSICC(myInputSignal))
/* synthesis syn_noprune=1 */;
* Supported in Libero IDE v7.2 and newer versions.
Figure 2-2 User Low Static (Idle) Mode Application—Internal Control Signal
Internal
Signal
ULSICC
Macro
FlashROM
Programming
Circuitry
ProASIC3/E Device