參數(shù)資料
型號: A3P125-VQG100T
元件分類: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
封裝: 0.50 MM PITCH, GREEN, VQFP-100
文件頁數(shù): 4/144頁
文件大?。?/td> 4877K
代理商: A3P125-VQG100T
Automotive ProASIC3 Flash Family FPGAs
R e visio n 1
2 - 89
Table 2-118 RAM512X18
Automotive-Case Conditions: TJ = 135°C, Worst-Case VCC = 1.425 V
Parameter
Description
–1
Std. Units
tAS
Address Setup Time
0.30 0.35
ns
tAH
Address Hold Time
0.00 0.00
ns
tENS
REN_B, WEN_B Setup Time
0.11 0.13
ns
tENH
REN_B, WEN_B Hold Time
0.07 0.08
ns
tDS
Input data (DI) Setup Time
0.22 0.26
ns
tDH
Input data (DI) Hold Time
0.00 0.00
ns
tCKQ1
Clock High to New Data Valid on DO (output retained, WMODE = 0)
2.58 3.03
ns
tCKQ2
Clock High to New Data Valid on DO (pipelined)
1.07 1.26
ns
tWRO
Address collision clk-to-clk delay for reliable read access after write on same
address
TBD TBD
ns
tCCKH
Address collision clk-to-clk delay for reliable write access after write/read on same
address
TBD TBD
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (flow-through)
1.10 1.29
ns
RESET_B Low to Data Out Low on DO (pipelined)
1.10 1.29
ns
tREMRSTB
RESET_B Removal
0.34 0.40
ns
tRECRSTB
RESET_B Recovery
1.79 2.10
ns
tMPWRSTB
RESET_B Minimum Pulse Width
0.25 0.30
ns
tCYC
Clock Cycle Time
3.85 4.53
ns
FMAX
Maximum Frequency
260
221
MHz
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-5 for derating values.
相關(guān)PDF資料
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A3P125-1FG144I FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PBGA144
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