5-4 Revision 13 Revision Changes Page Revision 9 (Oct 2009) Product Brief v1.3 The CS121 package was added to table under &q" />
參數(shù)資料
型號(hào): A3P400-2FGG484
廠商: Microsemi SoC
文件頁(yè)數(shù): 125/220頁(yè)
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 400K 484-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3
RAM 位總計(jì): 55296
輸入/輸出數(shù): 194
門數(shù): 400000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
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Datasheet Information
5-4
Revision 13
Revision
Changes
Page
Revision 9 (Oct 2009)
Product Brief v1.3
The CS121 package was added to table under "Features and Benefits" section,
I IV
"ProASIC3 Ordering Information" was revised to include the fact that some RoHS
compliant packages are halogen-free.
Packaging v1.5
The "CS121" figure and pin table for A3P060 are new.
Revision 8 (Aug 2009)
Product Brief v1.2
All references to M7 devices (CoreMP7) and speed grade –F were removed from
this document.
N/A
The "I/Os with Advanced I/O Standards" section was revised to add definitions of
hot-swap and cold-sparing.
DC and Switching
Characteristics v1.4
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
N/A
IIL and IIH input leakage current information was added to all "Minimum and
Maximum DC Input and Output Levels" tables.
N/A
–F was removed from the datasheet. The speed grade is no longer supported.
N/A
updated.
In Table 2-116 RAM4K9, the following specifications were removed:
tWRO
tCCKH
In Table 2-117 RAM512X18, the following specifications were removed:
tWRO
tCCKH
In the title of Table 2-74 1.8 V LVCMOS High Slew, VCCI had a typo. It was
changed from 3.0 V to 1.7 V.
Revision 7 (Feb 2009)
Product Brief v1.1
The "Advanced I/O" section was revised to add a bullet regarding wide range
power supply voltage support.
The table under "Features and Benefits" section, was updated to include a value
for typical equivalent macrocells for A3P250.
The QN48 package was added to the following tables: the table under "Features
The number of singled-ended I/Os for QN68 was added to the "I/Os Per
N/A
Revision 6 (Dec 2008)
Packaging v1.4
The "QN48" section is new.
The "QN68" pin table for A3P030 is new.
相關(guān)PDF資料
PDF描述
M1A3P400-2FG484 IC FPGA 1KB FLASH 400K 484-FBGA
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參數(shù)描述
A3P400-2FGG484I 功能描述:IC FPGA 1KB FLASH 400K 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:ProASIC3 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA(17x17)
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