Revision 13 2-21 3.3 V GTL+ 35 mA 12 – 2.5 V GTL+ 33 mA 15 – HSTL (I) 8 mA 50 HSTL (II) 15 mA
參數(shù)資料
型號: A3PE1500-2FG676
廠商: Microsemi SoC
文件頁數(shù): 92/162頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 1.5M 676-FBGA
標準包裝: 40
系列: ProASIC3E
RAM 位總計: 276480
輸入/輸出數(shù): 444
門數(shù): 1500000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
ProASIC3E Flash Family FPGAs
Revision 13
2-21
3.3 V GTL+
35 mA
12
2.5 V GTL+
33 mA
15
HSTL (I)
8 mA
50
HSTL (II)
15 mA 4
25
SSTL2 (I)
15 mA
27
31
SSTL2 (II)
18 mA
13
15
SSTL3 (I)
14 mA
44
69
SSTL3 (II)
21 mA
18
32
Table 2-20 I/O Weak Pull-Up/Pull-Down Resistances
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
VCCI
R((WEAK PULL-UP)1
(
)
R(WEAK PULL-DOWN)2
(
)
Min.
Max.
Min.
Max.
3.3 V
10 k
45 k
10 k
45 k
3.3 V (Wide
Range I/Os)
10 k
45 k
10 k
45 k
2.5 V
11 k
55 k
12 k
74 k
1.8 V
18 k
70 k
17 k
110 k
1.5 V
19 k
90 k
19 k
140 k
Notes:
1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN)
2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN)
Table 2-19 I/O Output Buffer Maximum Resistances1 (continued)
Standard
Drive Strength
RPULL-DOWN ()2
RPULL-UP ()3
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
values depend on VCCI, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at www.microsemi.com/soc/techdocs/models/ibis.html.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
4. Output drive strength is below JEDEC specification.
相關PDF資料
PDF描述
ACC49DREN-S93 CONN EDGECARD 98POS .100 EYELET
A3PE1500-2FGG676 IC FPGA 1KB FLASH 1.5M 676-FBGA
ABC49DREN-S93 CONN EDGECARD 98POS .100 EYELET
M1A3PE1500-2FG676 IC FPGA 1KB FLASH 1.5M 676-FBGA
ACC49DREH-S93 CONN EDGECARD 98POS .100 EYELET
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