2-60 Revision 13 Timing Characteristics Figure 2-31 Input DDR Timing Diagram
參數(shù)資料
型號(hào): A3PE1500-FG676I
廠商: Microsemi SoC
文件頁數(shù): 135/162頁
文件大?。?/td> 0K
描述: IC FPGA 1KB FLASH 1.5M 676-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3E
RAM 位總計(jì): 276480
輸入/輸出數(shù): 444
門數(shù): 1500000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 676-BGA
供應(yīng)商設(shè)備封裝: 676-FBGA(27x27)
ProASIC3E DC and Switching Characteristics
2-60
Revision 13
Timing Characteristics
Figure 2-31 Input DDR Timing Diagram
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRICLR2Q1
12
3
4
5
6
7
8
9
CLK
Data
CLR
Out_QR
Out_QF
tDDRICLKQ1
2
4
6
3
5
7
tDDRIHD
tDDRISUD
tDDRICLKQ2
Table 2-90 Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.39
0.44
0.52
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.27
0.31
0.37
ns
tDDRISUD
Data Setup for Input DDR
0.28
0.32
0.38
ns
tDDRIHD
Data Hold for Input DDR
0.00
ns
tDDRICLR2Q1
Asynchronous Clear to Out Out_QR for Input DDR
0.57
0.65
0.76
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.46
0.53
0.62
ns
tDDRIREMCLR
Asynchronous Clear Removal Time for Input DDR
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery Time for Input DDR
0.22
0.25
0.30
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.22
0.25
0.30
ns
tDDRICKMPWH
Clock Minimum Pulse Width High for Input DDR
0.36
0.41
0.48
ns
tDDRICKMPWL
Clock Minimum Pulse Width Low for Input DDR
0.32
0.37
0.43
ns
FDDRIMAX
Maximum Frequency for Input DDR
1404 1232 1048
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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