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參數(shù)資料
| 型號(hào)： | A3PE3000-2FG324I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 64/162頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 324-FBGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 系列： | ProASIC3E |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 221 |
| 門(mén)數(shù)： | 3000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 324-BGA |
| 供應(yīng)商設(shè)備封裝： | 324-FBGA（19x19） |
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Datasheet Information
5-6
Revision 13
v2.1
(continued)
The words "ambient temperature" were added to the temperature range in the
"Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix",
and "Speed Grade and Temperature Grade Matrix" sections.
iii, iv, iv
The "Clock Conditioning Circuit (CCC) and PLL" section was updated.
i
The caption "Main (chip)" in Figure 2-9 Overview of Automotive ProASIC3
VersaNet Global Network was changed to "Chip (main)."
2-9
The TJ parameter in Table 3-2 Recommended Operating Conditions was
changed to TA, ambient temperature, and table notes 4–6 were added.
3-2
The "PLL Macro" section was updated to add information on the VCO and PLL
outputs during power-up.
2-15
v2.0
(April 2007)
In the "Temperature Grade Offerings" section, Ambient was deleted.
iii
Ambient was deleted from "Temperature Grade Offerings".
iii
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
iv
The "PLL Macro" section was updated to include power-up information.
2-15
Table 2-13 ProASIC3E CCC/PLL Specification was updated.
2-30
Figure 2-19 Peak-to-Peak Jitter Definition is new.
2-18
The "SRAM and FIFO" section was updated with operation and timing
requirement information.
2-21
The "RESET" section was updated with read and write information.
2-25
The "RESET" section was updated with read and write information.
2-25
The "Introduction" in the "Advanced I/Os" section was updated to include
information on input and output buffers being disabled.
2-28
In the Table 2-15 Levels of Hot-Swap Support, the ProASIC3 compliance
descriptions were updated for levels 3 and 4.
2-34
Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E
Devices was updated.
2-64
Notes 3, 4, and 5 were added to Table 2-17 Comparison Table for 5 V–
Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum
current was updated from 4 x 52.7 to 5 x 52.7.
2-40
The "VCCPLF PLL Supply Voltage" section was updated.
2-50
The "VPUMP Programming Supply Voltage" section was updated.
2-50
The "GL Globals" section was updated to include information about direct input
into quadrant clocks.
2-51
VJTAG was deleted from the "TCK Test Clock" section.
2-51
In Table 2-22 Recommended Tie-Off Values for the TCK and TRST Pins, TSK
was changed to TCK in note 2. Note 3 was also updated.
2-51
Ambient was deleted from Table 3-2 Recommended Operating Conditions.
VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".
3-2
Note 3 is new in Table 3-4 Overshoot and Undershoot Limits (as measured on
quiet I/Os).
3-2
In EQ 3-2, 150 was changed to 110 and the result changed to 5.88.
3-5
Revision
Changes
Page
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| A3PE3000-2FG484 | 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3E 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A3PE3000-2FG484I | 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門(mén)數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
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