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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3PE3000-FG324I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 158/162闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 3M 324-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 84
绯诲垪锛� ProASIC3E
RAM 浣嶇附瑷�(j矛)锛� 516096
杓稿叆/杓稿嚭鏁�(sh霉)锛� 221
闁€鏁�(sh霉)锛� 3000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 324-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 324-FBGA锛�19x19锛�
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ProASIC3E Flash Family FPGAs
Revision 13
2-81
Timing Characteristics
Table 2-101 FIFO
Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tENS
REN, WEN Setup Time
1.38
1.57
1.84
ns
tENH
REN, WEN Hold Time
0.02
ns
tBKS
BLK Setup Time
0.19
0.22
0.26
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
0.18
0.21
0.25
ns
tDH
Input Data (WD) Hold Time
0.00
ns
tCKQ1
Clock High to New Data Valid on RD (pass-through)
2.36
2.68
3.15
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
0.89
1.02
1.20
ns
tRCKEF
RCLK High to Empty Flag Valid
1.72
1.96
2.30
ns
tWCKFF
WCLK High to Full Flag Valid
1.63
1.86
2.18
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
6.19
7.05
8.29
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
1.69
1.93
2.27
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
6.13
6.98
8.20
ns
tRSTBQ
RESET Low to Data Out Low on RD (pass-through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on RD (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB
RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle Time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency
310
272
231
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1A3PE3000-FG324I IC FPGA 1KB FLASH 3M 324-FBGA
M1A3PE3000-FGG324I IC FPGA 1KB FLASH 3M 324-FBGA
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