ProASIC3L Low Power Flash FPGAs
Revision 13
2-67
Table 2-95 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7V
Applicable to Standard Plus I/O Banks
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.70
7.21
0.05
1.17
0.50
7.35
6.14
2.03
1.32
9.36
8.16
ns
–1
0.60
6.13
0.04
0.99
0.43
6.25
5.23
1.72
1.12
7.96
6.94
ns
4 mA
Std.
0.70
5.81
0.05
1.17
0.50
5.92
5.26
2.39
2.25
7.93
7.27
ns
–1
0.60
4.94
0.04
0.99
0.43
5.03
4.47
2.03
1.91
6.74
6.19
ns
6 mA
Std.
0.70
4.96
0.05
1.17
0.50
5.05
4.65
2.64
2.69
7.06
6.66
ns
–1
0.60
4.22
0.04
0.99
0.43
4.30
3.96
2.25
2.29
6.01
5.67
ns
8 mA
Std.
0.70
4.96
0.05
1.17
0.50
5.05
4.65
2.64
2.69
7.06
6.66
ns
–1
0.60
4.22
0.04
0.99
0.43
4.30
3.96
2.25
2.29
6.01
5.67
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-96 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V
Applicable to Standard Plus I/O Banks
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
2 mA
Std.
0.70
3.22
0.05
1.08
0.50
3.28
3.04
2.02
1.37
5.30
5.06
ns
–1
0.60
2.74
0.04
0.92
0.43
2.79
2.59
1.72
1.17
4.50
4.30
ns
4 mA
Std.
0.70
2.48
0.05
1.08
0.50
2.53
2.25
2.38
2.34
4.54
4.26
ns
–1
0.60
2.11
0.92
0.43
2.15
1.92
2.03
1.99
3.86
3.63
ns
6 mA
Std.
0.70
2.17
0.05
1.08
0.50
2.21
1.86
2.64
2.79
4.22
3.87
ns
–1
0.60
1.85
0.04
0.92
0.43
1.88
1.58
2.24
2.37
3.59
3.29
ns
8 mA
Std.
0.70
2.17
0.05
1.08
0.50
2.21
1.86
2.64
2.79
4.22
3.87
ns
–1
0.60
1.85
0.04
0.92
0.43
1.88
1.58
2.24
2.37
3.59
3.29
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.