2-68 Revision 13 Timing Characteristics Table 2-95 A3PE600 Global Resource
參數(shù)資料
型號： A3PE600-1FG256I
廠商： Microsemi SoC
文件頁數(shù)： 144/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 256-FBGA
標(biāo)準(zhǔn)包裝： 90
系列： ProASIC3E
RAM 位總計： 110592
輸入/輸出數(shù)： 165
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
ProASIC3E DC and Switching Characteristics
2-68
Revision 13
Timing Characteristics
Table 2-95 A3PE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.83
1.04
0.94
1.18
1.11
1.39
ns
tRCKH
Input High Delay for Global Clock
0.81
1.06
0.93
1.21
1.09
1.42
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.25
0.28
0.33
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-96 A3PE1500 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
1.071.291.221.471.431.72
ns
tRCKH
Input High Delay for Global Clock
1.061.321.211.501.421.76
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.34
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-97 A3PE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
Min.1 Max.2 Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
1.411.621.601.851.882.17
ns
tRCKH
Input High Delay for Global Clock
1.401.661.591.891.872.22
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
0.75
0.85
1.00
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
0.85
0.96
1.13
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.29
0.35
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
相關(guān)PDF資料
PDF描述
GSC65DRTN-S93 CONN EDGECARD 130PS DIP .100 SLD
GMC65DRTN-S93 CONN EDGECARD 130PS DIP .100 SLD
GSC65DRTH-S93 CONN EDGECARD 130PS DIP .100 SLD
GMC65DRTH-S93 CONN EDGECARD 130PS DIP .100 SLD
ACC44DRYN-S13 CONN EDGECARD 88POS .100 EXTEND
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PE600-1FG484 功能描述:IC FPGA 600000 GATES 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A3PE600-1FG484I 功能描述:IC FPGA 600000 GATES 484-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A3PE600-1FG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1FG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1FG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*