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參數(shù)資料
| 型號(hào)： | A3PE600-2FG484 |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 66/162頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 600000 GATES 484-FBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | ProASIC3E |
| RAM 位總計(jì)： | 110592 |
| 輸入/輸出數(shù)： | 270 |
| 門(mén)數(shù)： | 600000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FPBGA（23x23） |
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Datasheet Information
5-8
Revision 13
Advance v0.5
(continued)
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
The "Introduction" of the "Introduction" section was updated.
2-28
PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-
11 VCCI Voltages and Compatible Standards
2-29
Table 2-35 ProASIC3E I/O Features was updated.
2-54
The "Double Data Rate (DDR) Support" section was updated to include
information concerning implementation of the feature.
2-32
The "Electrostatic Discharge (ESD) Protection" section was updated to include
testing information.
2-35
Level 3 and 4 descriptions were updated in Table 2-43 I/O Hot-Swap and 5 V
Input Tolerance Capabilities in ProASIC3 Devices.
2-64
The notes in Table 2-45 I/O Hot-Swap and 5 V Input Tolerance Capabilities in
ProASIC3E Devices were updated.
2-64
The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout"
section is new.
2-41
A footnote was added to Table 2-37 Maximum I/O Frequency for Single-Ended
and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength
and high slew selected).
2-55
Table 2-48 ProASIC3E I/O Attributes vs. I/O Standard Applications
2-81
Table 2-55 ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE)
Settings
2-85
The "x" was updated in the "Pin Descriptions" section.
2-50
The "VCC Core Supply Voltage" pin description was updated.
2-50
The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include
information concerning leaving the pin unconnected.
2-50
EXTFB was removed from Figure 2-24 ProASIC3E CCC Options.
2-24
The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table
2-13 ProASIC3E CCC/PLL Specification.
2-30
EXTFB was removed from Figure 2-27 CCC/PLL Macro.
2-28
The LVPECL specification in Table 2-45 I/O Hot-Swap and 5 V Input Tolerance
Capabilities in ProASIC3E Devices was updated.
2-64
Table 2-15 Levels of Hot-Swap Support was updated.
2-34
The "Cold-Sparing Support" section was updated.
2-34
"Electrostatic Discharge (ESD) Protection" section was updated.
2-35
The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"
section.
2-50
The "VJTAG JTAG Supply Voltage" pin description was updated.
2-50
The "VPUMP Programming Supply Voltage" pin description was updated to
include information on what happens when the pin is tied to ground.
2-50
Revision
Changes
Page
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PE600-2FG484I | 功能描述:IC FPGA 600000 GATES 484-FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A3PE600-2FG896 | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE600-2FG896ES | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE600-2FG896I | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE600-2FG896PP | 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
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