Revision 13 2-67 Global Resource Characteristics A3PE600 Clock Tree Topology Clock delays are device-specific. Figure" />
參數資料
型號: A3PE600-2FGG256
廠商: Microsemi SoC
文件頁數: 143/162頁
文件大?。?/td> 0K
描述: IC FPGA 600000 GATES 256-FBGA
標準包裝: 90
系列: ProASIC3E
RAM 位總計: 110592
輸入/輸出數: 165
門數: 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-LBGA
供應商設備封裝: 256-FPBGA(17x17)
ProASIC3E Flash Family FPGAs
Revision 13
2-67
Global Resource Characteristics
A3PE600 Clock Tree Topology
Clock delays are device-specific. Figure 2-38 is an example of a global tree used for clock routing. The
global tree presented in Figure 2-38 is driven by a CCC located on the west side of the A3PE600 device.
It is used to drive all D-flip-flops in the device.
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
page 2-68, and Table 2-97 on page 2-68 present minimum and maximum global clock delays within the
device. Minimum and maximum delays are measured with minimum and maximum loading.
Figure 2-38 Example of Global Tree Use in an A3PE600 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
相關PDF資料
PDF描述
A3PE600-2FG256 IC FPGA 600000 GATES 256-FBGA
A3PE600-FG484 IC FPGA 600000 GATES 484-FBGA
RSC50DRYN-S734 CONN EDGECARD 100PS DIP .100 SLD
RMC50DRYN-S734 CONN EDGECARD 100PS DIP .100 SLD
RSC50DRYH-S734 CONN EDGECARD 100PS DIP .100 SLD
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A3PE600-2FGG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
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