2-8 Revision 13 Power Consumption of Various Internal Resources SSTL3 (I) 30 3.3 26.02 114.87 SSTL3 (II" />
參數(shù)資料
型號： A3PE600-2FGG484
廠商： Microsemi SoC
文件頁數(shù)： 78/162頁
文件大?。?/td> 0K
描述： IC FPGA 600000 GATES 484-FBGA
標準包裝： 40
系列： ProASIC3E
RAM 位總計： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 484-BGA
供應商設備封裝： 484-FPBGA（23x23）
ProASIC3E DC and Switching Characteristics
2-8
Revision 13
Power Consumption of Various Internal Resources
SSTL3 (I)
30
3.3
26.02
114.87
SSTL3 (II)
30
3.3
42.21
131.76
Differential
LVDS/B-LVDS/M-LVDS
–
2.5
7.70
89.62
LVPECL
–
3.3
19.42
168.02
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Table 2-9 Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings (continued)
CLOAD
(pF)
VCCI
(V)
Static Power
PDC3 (mW)2
Dynamic Power
PAC10 (W/MHz)3
Table 2-10 Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices
Parameter
Definition
Device-Specific Dynamic Contributions
(W/MHz)
A3PE600
A3PE1500
A3PE3000
PAC1
Clock contribution of a Global Rib
12.77
16.21
19.7
PAC2
Clock contribution of a Global Spine
1.85
3.06
4.16
PAC3
Clock contribution of a VersaTile row
0.88
PAC4
Clock contribution of a VersaTile used as a sequential
module
0.12
PAC5
First contribution of a VersaTile used as a sequential
module
0.07
PAC6
Second contribution of a VersaTile used as a sequential
module
0.29
PAC7
Contribution of a VersaTile used as a combinatorial
module
0.29
PAC8
Average contribution of a routing net
0.70
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read
operation
25.00
PAC12
Average contribution of a RAM block during a write
operation
30.00
PAC13
Static PLL contribution
2.55 mW
PAC14
Dynamic contribution for PLL
2.60
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
calculator or SmartPower in Libero SoC.
相關PDF資料
PDF描述
IDT71V424S10YG IC SRAM 4MBIT 10NS 36SOJ
IDT71V416S12PHG IC SRAM 4MBIT 12NS 44TSOP
AFS250-2FGG256 IC FPGA 2MB FLASH 250K 256FBGA
M1AFS250-2FG256 IC FPGA 2MB FLASH 250K 256-FBGA
AFS250-2FG256 IC FPGA 2MB FLASH 250K 256FBGA
相關代理商/技術參數(shù)
參數(shù)描述
A3PE600-2FGG484I 功能描述:IC FPGA 600000 GATES 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA（27X27）
A3PE600-2FGG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FGG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FGG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-2FGG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*