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    參數(shù)資料
    

    


    


    
型號(hào)：
A3PN030-Z2QNG68I

    

    
元件分類：
FPGA

    

    
英文描述：
FPGA, 768 CLBS, 30000 GATES, QCC68

    

    
封裝：
8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-68

    

    
文件頁(yè)數(shù)：
1/100頁(yè)

    

    
文件大?。?/td>
3284K

    

    
代理商：
A3PN030-Z2QNG68I


    

    

    

	
    
    
    

    
    
	
    January 2010
    I
     2010 Actel Corporation
    ProASIC3 nano Flash FPGAs
    Features and Benefits
    Wide Range of Features
     10 k to 250 k System Gates
     Up to 36 kbits of True Dual-Port SRAM
     Up to 71 User I/Os
    Reprogrammable Flash Technology
     130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
     Live at Power-Up (LAPU) Level 0 Support
     Single-Chip Solution
     Retains Programmed Design when Powered Off
    High Performance
     350 MHz System Performance
    In-System Programming (ISP) and Security
     Secure ISP Using On-Chip 128-Bit Advanced Encryption
    Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
    FlashLock to Secure FPGA Contents
    Low Power
     Low-Power ProASIC3 nano Products
     1.5 V Core Voltage for Low Power
     Support for 1.5 V-Only Systems
     Low-Impedance Flash Switches
    High-Performance Routing Hierarchy
     Segmented, Hierarchical Routing and Clock Structure
    Advanced I/Os
     1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
     Bank-Selectable I/O Voltages—up to 4 Banks per Chip
     Single-Ended
    I/O
    Standards:
    LVTTL,
    LVCMOS
    3.3 V /
    2.5 V / 1.8 V / 1.5 V
     Wide Range Power Supply Voltage Support per JESD8-B,
    Allowing I/Os to Operate from 2.7 V to 3.6 V
     I/O Registers on Input, Output, and Enable Paths
     Selectable Schmitt Trigger Inputs
     Hot-Swappable and Cold-Sparing I/Os
     Programmable Output Slew Rate and Drive Strength
     Weak Pull-Up/-Down
     IEEE 1149.1 (JTAG) Boundary Scan Test
     Pin-Compatible Packages across the ProASIC3 Family
    Clock Conditioning Circuit (CCC) and PLL
     Up to Six CCC Blocks, One with an Integrated PLL
     Configurable Phase Shift, Multiply/Divide, Delay
    Capabilities and External Feedback
     Wide Input Frequency Range (1.5 MHz to 350 MHz)
    Embedded Memory
     1 kbit of FlashROM User Nonvolatile Memory
     SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
    Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
     True Dual-Port SRAM (except ×18 organization)
    Enhanced Commercial Temperature Range
     –20°C to +70°C
     A3PN030 and smaller devices do not support this feature.
    Table 1  ProASIC3 nano Devices
    ProASIC3 nano Devices
    A3PN010
    A3PN015
    A3PN020
    A3PN030 1
    A3PN060
    A3PN125
    A3PN250
    System Gates
    10 k
    15 k
    20 k
    30 k
    60 k
    125 k
    250 k
    Typical Equivalent Macrocells
    86
    128
    172
    256
    512
    1,024
    2,048
    VersaTiles (D-flip-flops)
    260
    384
    520
    768
    1,536
    3,072
    6,144
    RAM kbits (1,024 bits)2
    –
    18
    36
    4,608-Bit Blocks2
    –
    488
    FlashROM Bits
    1 k
    Secure (AES) ISP2
    –
    Yes
    Integrated PLL in CCCs2
    –
    111
    VersaNet Globals
    4
    6
    18
    I/O Banks
    2
    3
    2
    224
    Maximum User I/Os (packaged device)
    34
    49
    77
    71
    68
    Maximum User I/Os (Known Good Die)
    34
    –
    52
    83
    717168
    Package Pins
    QFN
    VQFP
    QN48
    QN68
    QN48, QN68
    VQ100
    Notes:
    1. A3PN030 is available in the Z feature grade only.
    2. A3PN030 and smaller devices do not support this feature.
    3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E handbooks.
    Advance v0.6
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
A3PN030-Z2QNG68
FPGA, 768 CLBS, 30000 GATES, QCC68

    

    
A3PN030-Z2VQ100I
FPGA, 768 CLBS, 30000 GATES, PQFP100

    

    
A3PN030-Z2VQ100
FPGA, 768 CLBS, 30000 GATES, PQFP100

    

    
A3PN030-Z2VQG100I
FPGA, 768 CLBS, 30000 GATES, PQFP100

    

    
A3PN030-Z2VQG100
FPGA, 768 CLBS, 30000 GATES, PQFP100

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
A3PN030-Z2VQ100
功能描述:IC FPGA NANO 30K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）

    

    
A3PN030-Z2VQ100I
功能描述:IC FPGA NANO 30K GATES 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）

    

    
A3PN030-Z2VQG100
功能描述:IC FPGA NANO 30K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）

    

    
A3PN030-Z2VQG100I
功能描述:IC FPGA NANO 30K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）

    

    
A3PN030-ZQNG48
功能描述:IC FPGA NANO 30K GATES 48-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）

    

    
    
    
    
	
    	
    
    
     
     
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