Revision 11 2-57 Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-73 " />
參數(shù)資料
型號(hào)： A3PN030-ZVQG100
廠商： Microsemi SoC
文件頁數(shù)： 84/114頁
文件大?。?/td> 0K
描述： IC FPGA NANO 30K GATES 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： ProASIC3 nano
輸入/輸出數(shù)： 77
門數(shù)： 30000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
ProASIC3 nano Flash FPGAs
Revision 11
2-57
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-73 ProASIC3 nano CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Delay Increments in Programmable Delay Blocks 1,2
2003
ps
Number of Programmable Values in Each Programmable Delay
Block
32
Serial Clock (SCLK) for Dynamic PLL 4,5
125
MHz
Input Cycle-to-Cycle Jitter (peak magnitude)
1.5
ns
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter 7
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay
1 1,2
1.25
15.65
ns
Delay Range in Block: Programmable Delay
2 1,2
0.025
15.65
ns
Delay Range in Block: Fixed Delay 1,2
2.2
ns
VCO Output Peak-to-Peak Period Jitter FCCC_OUT6
Max Peak-to-Peak Jitter Data 6,8,9
SSO
2
SSO
4
SSO
8SSO 16
0.75 MHz to 50MHz
0.50%
0.70%
1.00%
50 MHz to 250 MHz
1.00%
3.00%
5.00%
9.00%
250 MHz to 350 MHz
2.50%
4.00%
6.00%
12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help for more information.
4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
5. The A3PN010, A3PN015, and A3PN020 devices do not support PLLs.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings.
7. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
8. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI =
3.3 , VQ/PQ/TQ type of packages, 20 pF load.
9. SSOs are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ± 200 ps of
each other.
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