- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4473 > A40MX02-3VQG80I (Microsemi SoC)IC FPGA MX SGL CHIP 3K 80-VQFP PDF資料下載
參數(shù)資料
| 型號： | A40MX02-3VQG80I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 121/142頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA MX SGL CHIP 3K 80-VQFP |
| 標準包裝： | 90 |
| 系列： | MX |
| 輸入/輸出數(shù)： | 57 |
| 門數(shù)： | 3000 |
| 電源電壓： | 3 V ~ 3.6 V，4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 80-TQFP |
| 供應(yīng)商設(shè)備封裝： | 80-VQFP（14x14） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁當前第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁
40MX and 42MX FPGA Families
1- 4
R ev isio n 1 1
provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can
be used to implement registers for other user logic within the design.
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that may be continuous or split into segments.
Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
antifuse connections. Segments can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four
antifuses.
Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located
in between the rows of modules. Any segment that spans more than one-third of the row length is
considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing,
dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-
dedicated tracks are used for signal nets.
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks:
input, output, and long. Long tracks span the column length of the module, and can be divided into
multiple segments. Each segment in an input track is dedicated to the input of a particular module; each
segment in an output track is dedicated to the output of a particular module. Long segments are
Figure 1-4
A42MX24 and A42MX36 D-Module Implementation
Figure 1-5
A42MX36 Dual-Port SRAM Block
7 Inputs
Hard-Wire to I/O
Feedback to Array
Programmable
Inverter
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
Write
Port
Logic
RD[7:0]
Routing Tracks
Latches
Read
Logic
[5:0]
RDAD[5:0]
REN
RCLK
Latches
WD[7:0]
Latches
WRAD[5:0]
Write
Logic
MODE
BLKEN
WEN
WCLK
[5:0]
[7:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ASC31DRAN-S734 | CONN EDGECARD 62POS .100 R/A PCB |
| AGL400V2-CS196I | IC FPGA 1KB FLASH 400K 196-CSP |
| ASC31DRAH-S734 | CONN EDGECARD 62POS .100 R/A PCB |
| AGL400V2-CSG196I | IC FPGA 1KB FLASH 400K 196-CSP |
| FMC22DRXS | CONN EDGECARD 44POS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A40MX02-BG100 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A40MX02-BG100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A40MX02-BG100I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A40MX02-BG100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A40MX02-CQ100 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
發(fā)布緊急采購，3分鐘左右您將得到回復。