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  • 參數(shù)資料
    型號： A40MX04-3PLG68I
    廠商： Microsemi SoC
    文件頁數(shù)： 121/142頁
    文件大?。?/td> 0K
    描述： IC FPGA MX SGL CHIP 6K 68-PLCC
    標準包裝： 19
    系列： MX
    輸入/輸出數(shù)： 57
    門數(shù)： 6000
    電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
    安裝類型： 表面貼裝
    工作溫度： -40°C ~ 85°C
    封裝/外殼： 68-LCC（J 形引線）
    供應(yīng)商設(shè)備封裝： 68-PLCC（24.23x24.23）
    40MX and 42MX FPGA Families
    1- 4
    R ev isio n 1 1
    provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can
    be used to implement registers for other user logic within the design.
    Routing Structure
    The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
    modules. These routing tracks are metal interconnects that may be continuous or split into segments.
    Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
    antifuse connections. Segments can be joined together at the ends using antifuses to increase their
    lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four
    antifuses.
    Horizontal Routing
    Horizontal routing tracks span the whole row length or are divided into multiple segments and are located
    in between the rows of modules. Any segment that spans more than one-third of the row length is
    considered a long horizontal segment. A typical channel is shown in Figure 1-6. Within horizontal routing,
    dedicated routing tracks are used for global clock networks and for power and ground tie-off tracks. Non-
    dedicated tracks are used for signal nets.
    Vertical Routing
    Another set of routing tracks run vertically through the module. There are three types of vertical tracks:
    input, output, and long. Long tracks span the column length of the module, and can be divided into
    multiple segments. Each segment in an input track is dedicated to the input of a particular module; each
    segment in an output track is dedicated to the output of a particular module. Long segments are
    Figure 1-4
    A42MX24 and A42MX36 D-Module Implementation
    Figure 1-5
    A42MX36 Dual-Port SRAM Block
    7 Inputs
    Hard-Wire to I/O
    Feedback to Array
    Programmable
    Inverter
    SRAM Module
    32 x 8 or 64 x 4
    (256 Bits)
    Read
    Port
    Logic
    Write
    Port
    Logic
    RD[7:0]
    Routing Tracks
    Latches
    Read
    Logic
    [5:0]
    RDAD[5:0]
    REN
    RCLK
    Latches
    WD[7:0]
    Latches
    WRAD[5:0]
    Write
    Logic
    MODE
    BLKEN
    WEN
    WCLK
    [5:0]
    [7:0]
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    參數(shù)描述
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    A40MX04-3PLG84I 功能描述:IC FPGA MX SGL CHIP 6K 84-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
    A40MX04-3PQ100 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
    A40MX04-3PQ100I 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
    A40MX04-3PQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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