參數(shù)資料
型號： A40MX04-FPL44
元件分類： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 88/124頁
文件大?。?/td> 3142K
代理商： A40MX04-FPL44
40MX and 42MX FPGA Families
1- 60
v6.1
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.5
1.6
1.9
2.2
3.1
ns
tINYL
Pad-to-Y LOW
1.1
1.3
1.4
1.7
2.4
ns
tINGH
G to Y HIGH
2.0
2.2
2.5
2.9
4.1
ns
tINGL
G to Y LOW
2.0
2.2
2.5
2.9
4.1
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
2.6
2.9
3.2
3.8
5.3
ns
tIRD2
FO=2 Routing Delay
2.9
3.2
3.7
4.3
6.1
ns
tIRD3
FO=3 Routing Delay
3.3
3.6
4.1
4.9
6.8
ns
tIRD4
FO=4 Routing Delay
3.6
4.0
4.6
5.4
7.6
ns
tIRD8
FO=8 Routing Delay
5.1
5.6
6.4
7.5
10.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
4.4
4.8
5.3
5.5
6.0
6.5
7.1
9.0
9.9
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
tPWH
Minimum Pulse
Width HIGH
FO = 32
FO = 384
5.7
6.6
6.3
7.4
7.1
8.3
8.4
9.8
11.8
13.7
ns
tPWL
Minimum Pulse
Width LOW
FO = 32
FO = 384
5.3
6.2
5.9
6.9
6.7
7.9
7.8
9.2
11.0
12.9
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.5
2.2
0.5
2.4
0.6
2.7
0.7
3.2
1.0
4.5
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 384
3.9
4.5
4.3
4.9
5.6
5.7
6.6
8.0
9.2
ns
tP
Minimum Period
FO = 32
FO = 384
7.0
7.7
7.8
8.6
8.4
9.3
9.7
10.7
16.2
17.8
ns
fMAX
Maximum Frequency FO = 32
FO = 384
142
129
117
119
108
103
94
62
56
MHz
Table 35
A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 3.0V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Notes:
1. For dual-module macros use tPD1 + tRD1 + taped, to + tRD1 + taped, or tPD1 + tRD1 + tusk, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A40MX04-FPL68X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL68 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL84X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPL84 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPQ100X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100
相關代理商/技術參數(shù)
參數(shù)描述
A40MX04-FPL44I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL44M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL68 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
A40MX04-FPL68I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL68M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*