參數(shù)資料
型號(hào)： A40MX04-PL44MX79
元件分類： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 85/124頁
文件大?。?/td> 3142K
代理商： A40MX04-PL44MX79
40MX and 42MX FPGA Families
v6.1
1-57
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2
ns
tINYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
tINGH
G to Y HIGH
1.4
1.6
1.8
2.1
2.9
ns
tINGL
G to Y LOW
1.4
1.6
1.8
2.1
2.9
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
1.8
2.0
2.3
2.7
4.0
ns
tIRD2
FO=2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
tIRD3
FO=3 Routing Delay
2.3
2.6
3.0
3.5
4.9
ns
tIRD4
FO=4 Routing Delay
2.6
3.0
3.3
3.9
5.4
ns
tIRD8
FO=8 Routing Delay
3.6
4.0
4.6
5.4
7.5
ns
Global Clock Network
tCKH
Input LOW to HIGH
FO = 32
FO = 384
2.6
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
tCKL
Input HIGH to LOW
FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
6.6
7.8
9.2
ns
tPWH
Minimum
Pulse
Width HIGH
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
tPWL
Minimum
Pulse
Width LOW
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
0.3
0.4
0.5
0.7
ns
tSUEXT
Input Latch External
Set-Up
FO = 32
FO = 384
0.0
ns
tHEXT
Input Latch External
Hold
FO = 32
FO = 384
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
tP
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.6
5.8
6.4
9.7
10.7
ns
fMAX
Maximum
Frequency
FO = 32
FO = 384
237
215
195
198
179
172
156
103
94
MHz
Table 34
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A40MX04-PL44M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44X79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
A40MX04-PL44 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC44
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A40MX04-PL68I FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC68
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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A40MX04-PL68M 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 6K Gates 547 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 68-Pin PLCC 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 68PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 57 I/O 68PLCC 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC
A40MX04-PL68X4 制造商:Microsemi Corporation 功能描述:MX SERIES 6000 GATES FPGA
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