參數(shù)資料
型號(hào)： A40MX04-PQ100I
元件分類(lèi)： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 31/124頁(yè)
文件大?。?/td> 3142K
代理商： A40MX04-PQ100I
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40MX and 42MX FPGA Families
1- 8
v6.1
Power Dissipation
The general power consumption of MX devices is made
up of static and dynamic power and can be expressed
with the following equation:
General Power Equation
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N
+ IOH * (VCCI – VOH) * M
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS
switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
Static Power Component
The static power due to standby current is typically a
small component of the overall power consumption.
Standby power is calculated for commercial, worst-case
conditions. The static power dissipation by TTL loads
depends on the number of outputs driving, and on the
DC load current. For instance, a 32-bit bus sinking 4mA at
0.33V will generate 42mW with all outputs driving LOW,
and 140mW with all outputs driving HIGH. The actual
dissipation will average somewhere in between, as I/Os
switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. Dynamic power
consumption is frequency-dependent and is a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitances due to
PC board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect
can be associated with an equivalent capacitance that
can be combined with frequency and voltage to
represent active power dissipation.
The power dissipated by a CMOS circuit can be expressed
by the equation:
Power (W) = CEQ * VCCA
2 * F(1)
where:
CEQ =Equivalent capacitance expressed in picofarads (pF)
VCCA =Power supply in volts (V)
F =Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
CEQ Values for Actel MX FPGAs
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
Power = VCCA
2 * [(m x C
EQM * fm)Modules +
(n *
CEQI * fn)Inputs + (p * (CEQO + CL) *
fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 *
fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 *
fq2)routed_Clk2 (2)
where:
m
= Number
of
logic
modules
switching
at
frequency fm
n
= Number
of
input
buffers
switching
at
frequency fn
p
= Number
of
output
buffers
switching
at
frequency fp
q1
= Number of clock loads on the first routed array
clock
q2
= Number of clock loads on the second routed
array clock
r1
= Fixed capacitance due to first routed array
clock
r2
= Fixed capacitance due to second routed array
clock
相關(guān)PDF資料
PDF描述
A40MX04-PQ100MX79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100M FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100X79 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-PQ100 FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQFP100
A40MX04-VQ80AX79 FPGA, 547 CLBS, 6000 GATES, 116 MHz, PQFP80
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A40MX04-PQ100M 制造商:Microsemi Corporation 功能描述:FPGA 40MX Family 6K Gates 547 Cells 83MHz/139MHz 0.45um Technology 3.3V/5V 100-Pin PQFP 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 100PQFP - Trays 制造商:Microsemi SOC Products Group 功能描述:83MHZ/139MHZ 0.45UM TECHNOLOGY 3.3V/5V 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP
A40MX04-PQ208A 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families
A40MX04PQG100 制造商:Microsemi SOC Products Group 功能描述:
A40MX04-PQG100 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-PQG100A 功能描述:IC FPGA MX SGL CHIP 6K 100-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門(mén)數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
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