tIRD1 FO = 1" />
參數(shù)資料
型號(hào)： A40MX04-VQG80A
廠商： Microsemi SoC
文件頁數(shù)： 86/142頁
文件大小： 0K
描述： IC FPGA MX SGL CHIP 6K 80-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： MX
輸入/輸出數(shù)： 69
門數(shù)： 6000
電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 125°C
封裝/外殼： 80-TQFP
供應(yīng)商設(shè)備封裝： 80-VQFP（14x14）
40MX and 42MX FPGA Families
1- 44
R e v i sio n 1 1
Input Module Predicted Routing Delays1
tIRD1
FO = 1 Routing Delay
2.9
3.4
3.8
4.5
6.3
ns
tIRD2
FO = 2 Routing Delay
3.6
4.2
4.8
5.6
7.8
ns
tIRD3
FO = 3 Routing Delay
4.4
5.0
5.7
6.7
9.4
ns
tIRD4
FO = 4 Routing Delay
5.1
5.9
6.7
7.8
11.0
ns
tIRD8
FO = 8 Routing Delay
8.0
9.26
10.5
12.6
17.3
ns
Global Clock Network
tCKH
Input LOW to HIGH FO = 16
FO = 128
6.4
7.4
8.3
9.8
13.7
ns
tCKL
Input HIGH to LOW FO = 16
FO = 128
6.7
7.8
8.8
10.4
14.5
ns
tPWH
Minimum Pulse
Width HIGH
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tPWL
Minimum Pulse
Width LOW
FO = 16
FO = 128
3.1
3.3
3.6
3.8
4.1
4.3
4.8
5.1
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
0.6
0.8
0.6
0.9
0.7
1.0
0.8
1.2
1.6
ns
tP
Minimum Period
FO = 16
FO = 128
6.5
6.8
7.5
7.8
8.5
8.9
10.1
10.4
14.1
14.6
ns
fMAX
Maximum
Frequency
FO = 16
FO = 128
113
109
105
101
96
92
83
80
50
48
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
4.7
5.4
6.1
7.2
10.0
ns
tDHL
Data-to-Pad LOW
5.6
6.4
7.3
8.6
12.0
ns
tENZH
Enable Pad Z to HIGH
5.2
6.0
6.8
8.1
11.3
ns
tENZL
Enable Pad Z to LOW
6.6
7.6
8.6
10.1
14.1
ns
tENHZ
Enable Pad HIGH to Z
11.1
12.8
14.5
17.1
23.9
ns
tENLZ
Enable Pad LOW to Z
8.2
9.5
10.7
12.6
17.7
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.06
ns/pF
dTHL
Delta HIGH to LOW
0.04
0.05
0.06
0.08
ns/pF
Table 1-29 A40MX02 Timing Characteristics (Nominal 3.3 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min.
Max.
Min. Max. Min. Max. Min. Max. Min. Max. Units
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
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參數(shù)描述
A40MX04-VQG80I 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17）
A40MX04-VQG80M 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 80VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 6K 80-VQFP 制造商:Microsemi Corporation 功能描述:IC FPGA 69 I/O 80VQFP
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A-40P24 制造商:Pentair Technical Products / Hoffman 功能描述:Panel 37.00x21.00 fits 40.00x2 制造商:PENTAIR TECNICAL PRODCUTS 功能描述:Panel 37.00x21.00 fits 40.00x2
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