參數(shù)資料
型號(hào): A42MX02-1TQ100A
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁(yè)數(shù): 39/53頁(yè)
文件大小: 854K
代理商: A42MX02-1TQ100A
40MX and 42MX FPGA Families
1- 38
v6.0
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
3.3
3.8
4.3
5.1
7.2
ns
tDHL
Data-to-Pad LOW
4.0
4.6
5.2
6.1
8.6
ns
tENZH
Enable
Pad
Z
to
HIGH
3.7
4.3
4.9
5.8
8.0
ns
tENZL
Enable
Pad
Z
to
LOW
4.7
5.4
6.1
7.2
10.1
ns
tENHZ
Enable Pad HIGH to
Z
7.9
9.1
10.4
12.2
17.1
ns
tENLZ
Enable Pad LOW to
Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.02
0.03
0.04
ns/pF
dTHL
Delta HIGH to LOW
0.03
0.04
0.06
ns/pF
CMOS Output Module Timing4
tDLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
tDHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
tENZH
Enable
Pad
Z
to
HIGH
3.4
3.9
4.4
5.2
7.3
ns
tENZL
Enable
Pad
Z
to
LOW
4.9
5.6
6.4
7.5
10.5
ns
tENHZ
Enable Pad HIGH to
Z
7.9
9.1
10.4
12.2
17.0
ns
tENLZ
Enable Pad LOW to
Z
5.9
6.8
7.7
9.0
12.6
ns
dTLH
Delta LOW to HIGH
0.03
0.04
0.05
0.07
ns/pF
dTHL
Delta HIGH to LOW
0.02
0.03
0.04
ns/pF
Table 28
A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, VCC = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check the hold
time for this macro.
4. Delays based on 35pF loading.
相關(guān)PDF資料
PDF描述
A42MX04-1TQ100A 40MX and 42MX FPGA Families
A42MX09-1TQ100A Power Transformer; Series:VPS; Power Rating:43VA; Mounting Type:Chassis; Current Rating:3.4 Series/6.8 Prllel A; External Depth:2.000"; External Height:2.688"; External Width:3.125"; Leaded Process Compatible:No
A42MX16-1TQ100A 40MX and 42MX FPGA Families
A42MX24-1TQ100A XFRMR PWR 16.0VCT 11.0A QC .250
A42MX02-1TQ100B 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX02-1TQ100B 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families
A42MX02-1TQ100ES 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families
A42MX02-1TQ100I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families
A42MX02-1TQ100M 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families
A42MX02-1VQ100 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families