參數(shù)資料
型號： A42MX16-1TQ100A
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 65/120頁
文件大?。?/td> 854K
代理商： A42MX16-1TQ100A
49
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Note:
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programmed, interrupts are disabled while
executing from the Boot Loader section. Refer to Section 3.19 “Boot Loader Support -
Bit 0 - IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above.
3.11
External Interrupts
The Ext e rnal I n terrupts ar e t r igger ed by t he I N T0 pin or INT1 pin or any of the
PCINT23..16,10..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or
INT1 or PCINT23..16,10..0 pins are configured as outputs. This feature provides a way of gener-
ating a software interrupt. The pin change interrupt PCI2 will trigger if any enabled PCINT23..16
pin toggles. The pin change interrupt PCI1 will trigger if any enabled PCINT10..8 pin toggles. Pin
change interrupt PCI0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK2, PCMSK1
and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change
interrupts on PCINT23..16,10..0 are detected asynchronously. This implies that these interrupts
can be used for waking the part also from sleep modes other than Idle mode.
The INT0 or INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set
up as indicated in the specification for the External Interrupt Control Register A - EICRA. When
the INT0 or INT1 interrupt is enabled and is configured as level triggered, the interrupt will trigger
as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or
INT1 requires the presence of an I/O clock, described in Section 3.7.2 “Clock Systems and their
Distribution” on page 32. Low level interrupt on INT0 or INT1 is detected asynchronously. This
implies that this interrupt can be used for waking the part also from sleep modes other than Idle
mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT Fuses and CMM2..0 as described
相關(guān)PDF資料
PDF描述
A42MX24-1TQ100A XFRMR PWR 16.0VCT 11.0A QC .250
A42MX02-1TQ100B 40MX and 42MX FPGA Families
A42MX04-1TQ100B 40MX and 42MX FPGA Families
A42MX24-1VQ100A 40MX and 42MX FPGA Families
A42MX36-1VQ100A 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1TQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ176 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
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