參數(shù)資料
型號: A42MX16-2BG100
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 120/120頁
文件大小: 854K
代理商: A42MX16-2BG100
99
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-44. Transmit Mode with SSI, Timing Diagram
3.13.6.9
Mode 10: SPI Mode with the Outputs PD5 (T2O1), PD6 (T2O2) and PD7 (SDIN) Pins
The Timer2/Counter2 can be supplied with internal/external clocks. Mode 10 uses three modula-
tor I/O pins (SO --> T2O1, SCLK --> T2O2 and SI --> SDIN). The timer output clock (CLK
T2) can
be used to supply the SSI with shift clock. The SPI mode of the timer allows a SSI synchronous
data transfer between the ATA6289 and peripheral devices. The data is always shifted from
Master (SSI) to Slave on the Serial data Output line (SO) and from Slave to Master (SSI) on the
Serial data Input line (SI), synchronized to either the rising or falling edge of the shift clock output
line (SCLK). The Serial data is organized in 8-bit telegrams which are shifted with the most sig-
nificant bit (MSB) first on the serial data output line (SO). Figure 3-45 shows an example of a
three-wire synchronous serial data transfer.
Figure 3-45. SPI Mode with SSI, Timing Diagram
SCLK (T2CPOL = 0)
Internal
T2O2/SCLK
T1O1/SO
T2SSIE
T2MDR (TXD)
8-bit Shift Register (SR)
Load a new transmit value TXD
Load new
byte to SR
New byte
MS
0xC1
0x80
0x7F
0x40
0x20
0x10
0x08
0x04
0x82
0xC1
LSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
LSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
MSB first
SCKL (T2CPOL = 0)
Internal
SCKL (T2CPOL = 1)
Internal
T2O2 - PIN
SCKL (T2CPOL = 1)
SAMPLE -SI
SDIN - PIN
T2O1 - PIN
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