參數(shù)資料
型號： A42MX16-2PLG84I
廠商： Microsemi SoC
文件頁數(shù)： 53/142頁
文件大小： 0K
描述： IC FPGA MX SGL CHIP 24K 84-PLCC
標(biāo)準(zhǔn)包裝： 16
系列： MX
輸入/輸出數(shù)： 72
門數(shù)： 24000
電源電壓： 3 V ~ 3.6 V，4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC（29.31x29.31）
40MX and 42MX FPGA Families
1- 14
R e v i sio n 1 1
parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O
buffer to capture and load data into the register to control or observe the logic state of each I/O.
Figure 1-13 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 1-3
Test Access Port Descriptions
Port
Description
TMS
(Test Mode Select)
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic
clock (TCK).
TCK
(Test Clock Input)
Dedicated test logic clock used serially to shift test instruction, test data, and control inputs
on the rising edge of the clock, and serially to shift the output data on the falling edge of the
clock. The maximum clock frequency for TCK is 20 MHz.
TDI
(Test Data Input)
Serial input for instruction and test data. Data is captured on the rising edge of the test logic
clock.
TDO
(Test Data Output)
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive
state (high impedance) when data scanning is not in progress.
Table 1-4
Supported BST Public Instructions
Instruction
IR Code
(IR2.IR0)
Instruction
Type
Description
EXTEST
000
Mandatory
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
SAMPLE/PRELOAD
001
Mandatory
Allows a snapshot of the signals at the device pins to be captured
and examined during operation
HIGH Z
101
Optional
Tristates all I/Os to allow external signals to drive pins. Please refer to
the IEEE Standard 1149.1 specification.
CLAMP
110
Optional
Allows state of signals driven from component pins to be determined
from the Boundary-Scan Register. Please refer to the IEEE Standard
1149.1 specification for details.
BYPASS
111
Mandatory
Enables the bypass register between the TDI and TDO pins. The test
data passes through the selected device to adjacent devices in the
test chain.
Boundary Scan Register
Instruction
Decode
Control Logic
TAP Controller
Instruction
Register
Bypass
Register
TMS
TCK
TDI
Output
MUX
TDO
JTAG
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