參數(shù)資料
型號： A42MX16-3CQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Buffers and Line Drivers With 3-State Outputs 20-SSOP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 63/123頁
文件大?。?/td> 854K
代理商： A42MX16-3CQ100
40MX and 42MX FPGA Families
v6.0
1-57
Input Module Propagation Delays
t
INYH
Pad-to-Y HIGH
1.1
1.2
1.3
1.6
2.2
ns
t
INYL
Pad-to-Y LOW
0.8
0.9
1.0
1.2
1.7
ns
t
INGH
G to Y HIGH
1.4
1.6
1.8
2.1
2.9
ns
t
INGL
Input Module Predicted Routing Delays
2
G to Y LOW
1.4
1.6
1.8
2.1
2.9
ns
t
IRD1
FO=1 Routing Delay
1.8
2.0
2.3
2.7
4.0
ns
t
IRD2
FO=2 Routing Delay
2.1
2.3
2.6
3.1
4.3
ns
t
IRD3
FO=3 Routing Delay
2.3
2.6
3.0
3.5
4.9
ns
t
IRD4
FO=4 Routing Delay
2.6
3.0
3.3
3.9
5.4
ns
t
IRD8
Global Clock Network
FO=8 Routing Delay
3.6
4.0
4.6
5.4
7.5
ns
t
CKH
Input LOW to HIGH
FO = 32
FO = 384
2.6
2.9
2.9
3.2
3.3
3.6
3.9
4.3
5.4
6.0
ns
ns
t
CKL
Input HIGH to LOW
FO = 32
FO = 384
3.8
4.5
4.2
5.0
4.8
5.6
5.6
6.6
7.8
9.2
ns
ns
t
PWH
Minimum
Width HIGH
Pulse
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
t
PWL
Minimum
Width LOW
Pulse
FO = 32
FO = 384
3.2
3.7
3.5
4.1
4.0
4.6
4.7
5.4
6.6
7.6
ns
ns
t
CKSW
Maximum Skew
FO = 32
FO = 384
0.3
0.3
0.4
0.4
0.4
0.4
0.5
0.5
0.7
0.7
ns
ns
t
SUEXT
Input Latch External
Set-Up
FO = 32
FO = 384
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HEXT
Input Latch External
Hold
FO = 32
FO = 384
2.8
3.2
3.1
3.5
5.5
4.0
4.1
4.7
5.7
6.6
ns
ns
t
P
Minimum Period
FO = 32
FO = 384
4.2
4.6
4.67
5.1
5.1
5.6
5.8
6.4
9.7
10.7
ns
ns
f
MAX
Maximum
Frequency
FO = 32
FO = 384
237
215
215
195
198
179
172
156
103
94
MHz
MHz
Table 34
A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, point and position whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A42MX16-3CQ100A Octal Buffers and Line Drivers With 3-State Outputs 20-SSOP -40 to 85
A42MX16-3CQ100B Octal Buffers and Line Drivers With 3-State Outputs 20-SSOP -40 to 85
A42MX16-3CQ100ES Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85
A42MX16-3CQ100I Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85
A42MX16-3CQ100M Octal Buffers and Line Drivers With 3-State Outputs 20-SOIC -40 to 85
相關代理商/技術參數(shù)
參數(shù)描述
A42MX16-3CQ100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3CQ100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3CQ100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3CQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-3CQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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