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參數(shù)資料
| 型號： | A42MX16-FBG100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Octal Buffers and Line Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 68/123頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-FBG100 |
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40MX and 42MX FPGA Families
1-62
v6.0
Table 36
A42MX24 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Logic Module Combinatorial Functions
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
PD
Internal Array Module Delay
1.2
1.3
1.5
1.8
2.5
ns
t
PDD
Logic Module Predicted Routing Delays
2
Internal Decode Module Delay
1.4
1.6
1.8
2.1
3.0
ns
t
RD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.7
ns
t
RD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
t
RD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.6
ns
t
RD4
FO=4 Routing Delay
1.5
1.7
1.9
2.2
3.1
ns
t
RD5
Logic Module Sequential Timing
3, 4
FO=8 Routing Delay
2.4
2.7
3.0
3.6
5.0
ns
t
CO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
t
GO
Latch Gate-to-Output
1.2
1.3
1.5
1.8
2.5
ns
t
SUD
Flip-Flop (Latch) Set-Up Time
0.3
0.4
0.4
0.5
0.7
ns
t
HD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
t
RO
Flip-Flop (Latch) Reset-to-Output
1.4
1.6
1.8
2.1
2.9
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.3
6.5
9.0
ns
Input Module Propagation Delays
t
INPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
t
INGO
Input Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.6
ns
t
INH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
INSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
t
ILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-FBG100A | Octal Buffers and Line Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| A42MX16-FBG100B | Octal Buffers and Line Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| A42MX16-FBG100ES | Octal Buffers and Line Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| A42MX16-FBG100I | Octal Buffers and Line Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| A42MX16-FBG100M | Octal Buffers and Line Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-FBG100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-FBG100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-FBG100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-FBG100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-FBG100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
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