參數(shù)資料
型號： A42MX16-FCQ100M
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 58/123頁
文件大?。?/td> 854K
代理商： A42MX16-FCQ100M
40MX and 42MX FPGA Families
1-52
v6.0
Table 33
A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 3.0V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Logic Module Propagation Delays
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
PD1
Single Module
1.6
1.8
2.1
2.5
3.5
ns
t
CO
Sequential Clock-to-Q
1.8
2.0
2.3
2.7
3.8
ns
t
GO
Latch G-to-Q
1.7
1.9
2.1
2.5
3.5
ns
t
RS
Logic Module Predicted Routing Delays
2
Flip-Flop (Latch) Reset-to-Q
2.0
2.2
2.5
2.9
4.1
ns
t
RD1
FO=1 Routing Delay
1.0
1.1
1.2
1.4
2.0
ns
t
RD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
t
RD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.3
ns
t
RD4
FO=4 Routing Delay
1.9
2.1
2.4
2.9
4.0
ns
t
RD8
Logic Module Sequential Timing
3, 4
FO=8 Routing Delay
3.2
3.6
4.1
4.8
6.7
ns
t
SUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
t
HD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
4.7
5.3
6.0
7.0
9.8
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
6.2
6.9
7.8
9.2
12.9
ns
t
A
Flip-Flop Clock Input Period
5.0
5.6
6.2
7.1
9.9
ns
t
INH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
INSU
Input Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
t
OUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
OUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
f
MAX
Flip-Flop (Latch) Clock
Frequency
161
146
135
117
70
MHz
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關PDF資料
PDF描述
A42MX16-FPL100 Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100A Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100B Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100ES Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100I Octal Transparent D-Type Latches With 3-State Outputs 20-PDIP -40 to 85
相關代理商/技術參數(shù)
參數(shù)描述
A42MX16-FPL100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*