參數(shù)資料
型號(hào)： A42MX16-FPL100
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 121/123頁(yè)
文件大?。?/td> 854K
代理商： A42MX16-FPL100
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FPGA Families 40MX and 42MX
v6.0
3-1
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
Changes in current version (v6.0)
Page
v5.1
The
"Ease of Integration" section
was updated.
1-i
The
"Temperature Grade Offerings" section
is new.
1-iii
The
"Speed Grade Offerings" section
is new.
1-iii
The
"General Description" section
was updated.
1-1
The
"MultiPlex I/O Modules" section
was updated.
1-6
The
"User Security" section
was updated.
1-6
Table 1 Voltage Support of MX Devices
was updated.
1-7
The
"Power Dissipation" section
was updated.
1-8
The
"Static Power Component" section
was updated.
1-8
The
"Equivalent Capacitance" section
was updated.
1-8
Figure 1-13 Silicon Explorer II Setup with 42MX
was updated.
1-10
Table 4 Supported BST Public Instructions
was updated.
1-11
Figure 1-14 42MX IEEE 1149.1 Boundary Scan Circuitry
was updated.
1-11
Table 5 Boundary Scan Pin Configuration and Functionality
was updated.
1-12
The
"Development Tool Support" section
was updated.
1-13
The
Table 7 Absolute Maximum Ratings for 42MX Devices*
and the
Table 6 Absolute
Maximum Ratings for 40MX Devices*
were updated.
1-14
The
Table 9 5V TTL Electrical Specifications
was updated.
1-15
The
Table 13 3.3V LVTTL Electrical Specifications
was updated.
1-17
In the
"Mixed 5.0V/3.3V Electrical Specifications" section
,
Table 14 Absolute Maximum
Ratings*
,
Table 15 Recommended Operating Conditions
, and
Table 16 Mixed 5.0V/3.3V
Electrical Specifications
were updated.
The
Table 17 DC Specification (5.0V PCI Signaling)
1
was updated.
The
Table 19 DC Specification (3.3V PCI Signaling)
1
was updated.
1-18
1-19
1-20
The <zBlue>Junction Temperature (T
J
) section,
"Package Thermal Characteristics" section
, and the
tables were updated.
1-22
Figure 1-17 40MX Timing Model*
was updated.
1-23
Figure 1-19 42MX Timing Model (Logic Functions Using Quadrant Clocks)
1-24
The
Figure 1-20 42MX Timing Model (SRAM Functions)
was updated.
1-24
The
Figure 1-27 Output Buffer Latches
was updated.
1-27
The
Table 22 42MX Temperature and Voltage Derating Factors
is new.
1-31
The
Table 23 40MX Temperature and Voltage Derating Factors
is new.
1-32
The
"Pin Descriptions" section
was updated.
1-77
In the
100-Pin PQFP
table, the following pins changed:
Pin 64 (42MX09 and 42MX16) has changed to LP
2-7
相關(guān)PDF資料
PDF描述
A42MX16-FPL100A Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100B Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100ES Octal Transparent D-Type Latches With 3-State Outputs 20-SOIC -40 to 85
A42MX16-FPL100I Octal Transparent D-Type Latches With 3-State Outputs 20-PDIP -40 to 85
A42MX16-FPL100M 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-FPL100A 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100ES 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100I 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-FPL100M 制造商:ACTEL 制造商全稱(chēng):Actel Corporation 功能描述:40MX and 42MX FPGA Families
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