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參數(shù)資料
| 型號： | A42MX16-FVQG100 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 130/142頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA MX SGL CHIP 24K 100-VQFP |
| 標準包裝： | 90 |
| 系列： | MX |
| 輸入/輸出數(shù)： | 83 |
| 門數(shù)： | 24000 |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-VQFP（14x14） |
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40MX and 42MX FPGA Families
1- 84
R e v i sio n 1 1
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW.
SDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device programming. SDO is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is LOW. SDO is available for 42MX devices only.
When Silicon Explorer II is being used, SDO will act as an output while the "checksum" command is run.
It will return to user I/O when "checksum" is complete.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data into the device. This pin functions as an I/O
when "Reserve JTAG" is not checked in the Designer Software. BST pins are only available in A42MX24
and A42MX36 devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is shifted in on the rising edge of TCK. This pin
functions as an I/O when "Reserve JTAG" is not checked in the Designer Software. BST pins are only
available in A42MX24 and A42MX36 devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This pin functions as an I/O when "Reserve JTAG"
is not checked in the Designer Software. BST pins are only available in A42MX24 and A42MX36
devices.
TMS, I/O
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins are boundary scan pins. Once the boundary
scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine
reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as
regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In
dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10k
Ω pull-up resistor on the pin. BST pins are only available in A42MX24
and A42MX36 devices.
VCC
Supply Voltage
Input supply voltage for 40MX devices
VCCA
Supply Voltage
Supply voltage for array in 42MX devices
VCCI
Supply Voltage
Supply voltage for I/Os in 42MX devices
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device this pin can be used as a dedicated output from
the wide decode module. This direct connection eliminates additional interconnect delays associated
with regular logic modules. To implement the direct I/O connection, connect an output buffer of any type
to the output of the wide decode macro and place this output on one of the reserved WD pins.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-PL100 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-PL100ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-PL100I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-PL100M | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX FPGA Families |
| A42MX16-PL208A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:40MX and 42MX Automotive FPGA Families |
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