參數(shù)資料
型號(hào)： A42MX24-1TQ100ES
廠商： Electronic Theatre Controls, Inc.
英文描述： Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:25VA; Mounting Type:Chassis; External Depth:1.938"; External Height:2.313"; External Width:2.813"; Leaded Process Compatible:Yes
中文描述： 40MX和42MX FPGA系列
文件頁(yè)數(shù)： 20/93頁(yè)
文件大小： 854K
代理商： A42MX24-1TQ100ES
27
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
RT MEMORY MANAGEMENT
The Mini-ACE Mark3 provides a variety of RT memory manage-
ment capabilities. As with the ACE and Mini-ACE, the choice of
memory management scheme is fully programmable on a trans-
mit/receive/broadcast subaddress basis.
In compliance with MIL-STD-1553B Notice 2, received data from
broadcast messages may be optionally separated from non-
broadcast received data. For each transmit, receive or broadcast
subaddress, either a single-message data block, a double
buffered configuration (two alternating Data Word blocks), or a
variable-sized (128 to 8192 words) subaddress circular buffer
may be allocated for data storage. The memory management
scheme for individual subaddresses is designated by means of
the subaddress control word (reference TABLE 40).
For received data, there is also a global circular buffer mode. In
this configuration, the data words received from multiple (or all)
subaddresses are stored in a common circular buffer structure.
Like the subaddress circular buffer, the size of the global circular
buffer is programmable, with a range of 128 to 8192 data words.
The double buffering feature provides a means for the host
processor to easily access the most recent, complete received
block of valid Data Words for any given subaddress. In addition
to helping ensure data sample consistency, the circular buffer
options provide a means for greatly reducing host processor
overhead for multi-message bulk data transfer applications.
End-of-message interrupts may be enabled either globally (fol-
lowing all messages), following error messages, on a
transmit/receive/broadcast subaddress or mode code basis, or
when a circular buffer reaches its midpoint (50% boundary) or
lower (100%) boundary. A pair of interrupt status registers allow
the host processor to determine the cause of all interrupts by
means of a single read operation.
Subaddress -
specific circular buffer
of specified size.
8192-Word
1
(for receive and / or broadcast subaddresses only)
Global Circular Buffer: The buffer size is specified by
Configuration Register #6, bits 11-9. The pointer to the global
circular buffer is stored at address 0101 (for Area A) or address
0105 (for Area B)
1
0
1
4096-Word
0
1
0
1
1024-Word
0
1
512-Word
1
0
256-Word
0
1
0
128-Word
1
0
For Receive or Broadcast:
Double Buffered
For Transmit: Single Message
Single Message
0
1
0
SUBADDRESS CONTROL WORD BITS
MM0
MEMORY MANAGEMENT SUBADDRESS
BUFFER SCHEME DESCRIPTION
MM1
DOUBLE-BUFFERED OR
GLOBAL CIRCULAR BUFFER
(bit 15)
MM2
TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS
2048-Word
1
0
1
相關(guān)PDF資料
PDF描述
A42MX02-1TQ100I Power Transformer; Series:VPS; Power Rating:43VA; Mounting Type:Chassis; Current Rating:0.19 Series/0.38 Prllel A; External Depth:2.000"; External Height:2.688"; External Width:3.125"; Leaded Process Compatible:No RoHS Compliant: Yes
A42MX04-1TQ100I Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:80VA; Mounting Type:Chassis; Current Rating:0.35 Series/0.7 Prllel AA; External Depth:2.313"; External Height:3.000"; External Width:2.500"
A42MX09-1TQ100I XFRMR PWR 230.0VCT 0.57A QC .250
A42MX02-1VQ100 XFRMR PWR 28.0VCT 4.6A QC .250
A42MX04-1VQ100 XFRMR PWR 28.0VCT 6.25A QC .250
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX24-1TQ176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1TQ176I 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1TQ176M 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 176TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 150 I/O 176TQFP
A42MX24-1TQG176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX24-1TQG176I 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門(mén)數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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