參數資料
型號： A42MX24-1TQ100I
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數： 14/123頁
文件大小： 854K
代理商： A42MX24-1TQ100I
40MX and 42MX FPGA Families
1-8
v6.0
Power Dissipation
The general power consumption of MX devices is made
up of static and dynamic power and can be expressed
with the following equation:
General Power Equation
P = [I
CC
standby + I
CC
active] * V
CCI
+ I
OL
* V
OL
* N
+ I
OH
* (V
CCI
– V
OH
) * M
where:
I
CC
standby is the current flowing when no inputs or
outputs are changing.
I
CC
active is the current flowing due to CMOS
switching.
I
OL
, I
OH
are TTL sink/source currents.
V
OL
, V
OH
are TTL level output voltages.
N equals the number of outputs driving TTL loads to
V
OL
.
M equals the number of outputs driving TTL loads to
V
OH
.
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
Static Power Component
The static power due to standby current is typically a
small component of the overall power consumption.
Standby power is calculated for commercial, worst-case
conditions. The static power dissipation by TTL loads
depends on the number of outputs driving, and on the
DC load current. For instance, a 32-bit bus sinking 4mA at
0.33V will generate 42mW with all outputs driving LOW,
and 140mW with all outputs driving HIGH. The actual
dissipation will average somewhere in between, as I/Os
switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. Dynamic power
consumption is frequency-dependent and is a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitances due to
PC board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect
can be associated with an equivalent capacitance that
can be combined with frequency and voltage to
represent active power dissipation.
The power dissipated by a CMOS circuit can be expressed
by the equation:
Power (μW) = C
EQ
* V
CCA2
* F(1)
where:
C
EQ
=Equivalent capacitance expressed in picofarads (pF)
V
CCA
=Power supply in volts (V)
F =Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring
I
CC
active at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of
V
CC
.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
C
EQ
Values for Actel MX FPGAs
Modules (C
EQM
)3.5
Input Buffers (C
EQI
)6.9
Output Buffers (C
EQO
)18.2
Routed Array Clock Buffer Loads (C
EQCR
)1.4
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
Power = V
CCA2
* [(m x
C
EQM
* f
m
)
Modules
+
(n *
C
EQI
* f
n
)
Inputs
+ (p * (
C
EQO
+ C
L
) *
f
p
)
outputs
+
0.5 * (q
1
*
C
EQCR
* f
q1
)
routed_Clk1
+ (r
1
*
f
q1
)
routed_Clk1
+
0.5 * (q
2
*
C
EQCR
* f
q2
)
routed_Clk2
+ (r
2
*
f
q2
)
routed_Clk2
(2)
where:
m
= Number of logic modules switching at
frequency f
m
n
= Number
of
input
frequency f
n
p
= Number of output buffers switching at
frequency f
p
q
1
= Number of clock loads on the first routed array
clock
q
2
= Number of clock loads on the second routed
array clock
r
1
= Fixed capacitance due to first routed array
clock
r
2
= Fixed capacitance due to second routed array
clock
buffers
switching
at
相關PDF資料
PDF描述
A42MX24-1TQ100M 40MX and 42MX FPGA Families
A42MX16 Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SO -40 to 85
A42MX16-1PQ100I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-SO -40 to 85
A42MX16-1PQ100M Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
A42MX16-1TQ100I Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs 20-TSSOP -40 to 85
相關代理商/技術參數
參數描述
A42MX24-1TQ176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數:9360 邏輯元件/單元數:149760 RAM 位總計:6635520 輸入/輸出數:270 門數:- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
A42MX24-1TQ176I 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數:9360 邏輯元件/單元數:149760 RAM 位總計:6635520 輸入/輸出數:270 門數:- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
A42MX24-1TQ176M 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 176TQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 150 I/O 176TQFP
A42MX24-1TQG176 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數:9360 邏輯元件/單元數:149760 RAM 位總計:6635520 輸入/輸出數:270 門數:- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
A42MX24-1TQG176I 功能描述:IC FPGA MX SGL CHIP 36K 176-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:MX 產品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數:9360 邏輯元件/單元數:149760 RAM 位總計:6635520 輸入/輸出數:270 門數:- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設備封裝:484-FBGA（23x23）
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