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參數(shù)資料
| 型號： | A42MX24-2PQ100B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 49/93頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX24-2PQ100B |
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53
Data Device Corporation
www.ddc-web.com
BU-6474X/6484X/6486X
J-07/05-0
POL_SEL (I) /
DTACK (O)
35
Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR should be asserted high (logic "1")
for a read operation and low (logic "0") for a write operation. In 16-bit buffered mode, if POL_SEL is con-
nected to logic "0", RD/WR should be asserted low (logic "0") for a read operation and high (logic "1") for a
write operation.
In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"), POL_SEL input signal used to
control the logic sense of the MSB/LSB signal. If POL_SEL is connected to logic "0", MSB/LSB should be
asserted low (logic "0") to indicate the transfer of the least significant byte and high (logic "1") to indicate
the transfer of the most significant byte. If POL_SEL is connected to logic "1", MSB/LSB should be asserted
high (logic "1") to indicate the transfer of the least significant byte and low (logic "0") to indicate the transfer
of the most significant byte.
In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM
interface bus in response to a data transfer grant (DTGRT). Mark3 RAM transfers over A15-A0 and D15-D0
will be framed by the time that DTACK is asserted low.
TRIG_SEL (I) /
MEMENA_IN (I)
34
Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which byte pairs are transferred
to or from the Mark3 by the host processor. In the 8-bit buffered mode, TRIG_SEL should be asserted high
(logic 1) if the byte order for both read operations and write operations is MSB followed by LSB. TRIG_SEL
should be asserted low (logic 0) if the byte order for both read operations and write operations is LSB fol-
lowed by MSB.
This signal has no operation in the 16-bit buffered mode (it does not need to be connected).
In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Mark3's inter-
nal shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that is
OR'ing the DTACK and IOEN output signals.
MEM / REG(I)
6
Memory/Register.
Generally connected to either a CPU address line or address decoder output. Selects between memory
access (MEM/REG = "1") or register access (MEM/REG = "0").
TRANSPARENT/
BUFFERED (I)
61
Used to select between the buffered mode (when strapped to logic "0") and transparent/DMA mode (when
strapped to logic "1") for the host processor interface.
SSFLAG (I) /
EXT_TRIG(I)
37
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the Mark3's RT Status Word.
If the SSFLAG input is logic "0" while bit 8 of Configuration Register #1 has been programmed to logic "1"
(cleared), the Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of Configuration Register
#1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the sense on the SSFLAG input has no
effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the exter-
nal BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will
issue a BC Start command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Mark3
BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to
high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
TABLE 53. PROCESSOR INTERFACE CONTROL (CONT.)
SIGNAL NAME
DESCRIPTION
BU-6474XF/GX
BU-6484XF/GX
BU-64863F/GX
PIN
FLAT PACK AND GULL WING PACKAGES - SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS (CONT.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100A | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2VQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX24-2PQ160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2PQ160I | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2PQ208 | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2PQ208I | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-2PQG160 | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FBGA（23x23） |
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