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| 型號(hào)： | A42MX24-2TQ176M |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（FPGA） |
| 文件頁(yè)數(shù)： | 49/116頁(yè) |
| 文件大?。?/td> | 3110K |
| 代理商： | A42MX24-2TQ176M |
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v5.0
49
40MX and 42MX FPGA Families
A42MX09 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
CC
= 3.0V, T
J
= 70
°
C)
‘–
3
’
Speed
‘–
2
’
Speed
‘–
1
’
Speed
‘
Std
’
Speed
‘–
F
’
Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays
1
t
PD1
Single Module
1.6
1.8
2.1
2.5
3.5
ns
t
CO
Sequential Clock-to-Q
1.8
2.0
2.3
2.7
3.8
ns
t
GO
Latch G-to-Q
1.7
1.9
2.1
2.5
3.5
ns
t
RS
Logic Module Predicted Routing Delays
2
Flip-Flop (Latch) Reset-to-Q
2.0
2.2
2.5
2.9
4.1
ns
t
RD1
FO=1 Routing Delay
1.0
1.1
1.2
1.4
2.0
ns
t
RD2
FO=2 Routing Delay
1.3
1.4
1.6
1.9
2.7
ns
t
RD3
FO=3 Routing Delay
1.6
1.8
2.0
2.4
3.3
ns
t
RD4
FO=4 Routing Delay
1.9
2.1
2.4
2.9
4.0
ns
t
RD8
Logic Module Sequential Timing
3, 4
FO=8 Routing Delay
3.2
3.6
4.1
4.8
6.7
ns
t
SUD
Flip-Flop (Latch) Data Input Set-Up
0.5
0.5
0.6
0.7
0.9
ns
t
HD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
0.0
0.0
0.0
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
0.6
0.6
0.7
0.8
1.2
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.7
5.3
6.0
7.0
9.8
ns
t
WASYN
Flip-Flop (Latch) Asynchronous Pulse
Width
6.2
6.9
7.8
9.2
12.9
ns
t
A
Flip-Flop Clock Input Period
5.0
5.6
6.2
7.1
9.9
ns
t
INH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
INSU
Input Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
t
OUTH
Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
OUTSU
Output Buffer Latch Set-Up
0.3
0.3
0.3
0.4
0.6
ns
f
MAX
Flip-Flop (Latch) Clock
Frequency
161
146
135
117
70
MHz
Notes:
1.
2.
For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the Timer utility.
Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
3.
4.
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