參數(shù)資料
型號： A42MX24-3PQ100I
廠商： Electronic Theatre Controls, Inc.
英文描述： Octal Bus Transceivers With 3-State Outputs 20-PDIP -40 to 85
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 18/123頁
文件大?。?/td> 854K
代理商： A42MX24-3PQ100I
40MX and 42MX FPGA Families
1-12
v6.0
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools -> Device Selection. This
brings up the Device Selection dialog box as shown in
Figure 1-15
. The JTAG test logic circuit can be enabled by
clicking the "Reserve JTAG Pins" check box.
Table 5
explains the pins' behavior in either mode.
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Boundary Scan Description Language
(BSDL) File
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to
Format
相關(guān)PDF資料
PDF描述
A42MX24-3PQ100M Octal Bus Transceivers With 3-State Outputs 20-SO -40 to 85
A42MX24-3TQ100ES Octal Bus Transceivers With 3-State Outputs 20-SO -40 to 85
A42MX24-3TQ100I 40MX and 42MX FPGA Families
A42MX24-3TQ100M Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
A42MX24-3VQ100ES Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85
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A42MX24-3PQ208IPM79 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 208PQFP - Trays
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