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| 型號： | A42MX24-FTQ100I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SOIC -40 to 85 |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 12/123頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX24-FTQ100I |
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40MX and 42MX FPGA Families
1-6
v6.0
MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0V,
3.3V, and mixed 3.3V/5.0V operations.
The MultiPlex I/O modules provide the interface between
the device pins and the logic array.
Figure 1-9
is a block
diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can
be implemented in the module. (Refer to the
Macro Library Guidelatches that can be configured for input, output, or
bidirectional operation.
All 42MX devices contain flexible I/O structures, where
each output pin has a dedicated output-enable control
(
Figure 1-9
). The I/O module can be used to latch input or
output data, or both, providing fast set-up time. In
addition, the Actel Designer software tools can build a D-
type flip-flop using a C-module combined with an I/O
module to register input and output signals. Refer to the
Antifuse Macro Library Guide
for more details.
A42MX24 and A42MX36 devices also offer selectable PCI
output drives, enabling 100% compliance with version
2.1 of the PCI specification. For low-power systems, all
inputs and outputs are turned off to reduce current
consumption to below 500
μ
A.
To achieve 5.0V or 3.3V PCI-compliant output drives on
A42MX24 and A42MX36 devices, a chip-wide PCI fuse is
programmed via the Device Selection Wizard in the
Designer software (
Figure 1-10
). When the PCI fuse is not
programmed, the output drive is standard.
Actel's Designer software development tools provide a
design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
Other Architectural Features
Performance
MX devices can operate with internal clock frequencies
of 250 MHz, enabling fast execution of complex logic
functions. MX devices are live on power-up and do not
require auxiliary configuration devices and thus are an
optimal
platform
to
integrate
contained in multiple programmable logic devices. In
addition, designs that previously would have required a
gate array to meet performance can be integrated into
an MX device with improvements in cost and time-to-
market. Using timing-driven place-and-route (TDPR)
tools, designers can achieve highly deterministic device
performance.
the
functionality
User Security
The Actel FuseLock provides robust security against
design theft. Special security fuses are hidden in the
fabric of the device and prevent unauthorized users from
accessing the programming and/or probe interfaces. It is
virtually impossible to identify or bypass these fuses
without damaging the device, making Actel antifuse
FPGAs immune to both invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe
Fuse and Program Fuse. The former disables the probing
circuitry while the latter prohibits further programming
of all fuses, including the Probe Fuse. In 42MX devices,
there is the Security Fuse which, when programmed,
both disables the probing circuitry and prohibits further
programming of the device.
Look for this symbol to ensure your valuable IP is secure.
For more information, refer to
Actel's Implementation of
Security in Actel Antifuse FPGAs
application note.
Note:
*Can be configured as a Latch or D Flip-Flop (Using
C-Module)
Figure 1-9
42MX I/O Module
Q
D
From Array
To Array
G/CLK*
G/CLK*
Q
D
PAD
EN
Figure 1-10
PCI Output Structure of A42MX24 and
A42MX36 Devices
Signal
PCI Enable
Fuse
PCI
Drive
STD
Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-FTQ100M | Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset 14-SSOP -40 to 85 |
| A42MX36-FCQ100M | 40MX and 42MX FPGA Families |
| A42MX36-FPL100 | 40MX and 42MX FPGA Families |
| A42MX36-FPL100A | 40MX and 42MX FPGA Families |
| A42MX36-FPL100B | 40MX and 42MX FPGA Families |
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