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參數(shù)資料
| 型號： | A42MX24-PQ208 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 76/142頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA MX SGL CHIP 36K 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MX |
| 輸入/輸出數(shù)： | 176 |
| 門數(shù)： | 36000 |
| 電源電壓： | 3 V ~ 3.6 V，4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
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40MX and 42MX FPGA Families
Re vi s i on 11
1 - 35
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends on the resistive and capacitive loading of the routing
tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as
the length of routing tracks, the number of interconnect elements, or the number of inputs increases.
From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing
tracks.
The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the
delay of the interconnect elements and by decreasing the number of interconnect elements per path.
Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses,
fabricated in 0.45 m lithography, offer nominal levels of 100
Ω resistance and 7.0 fF capacitance per
antifuse.
MX fanout distribution is also tight due to the low number of antifuses required for each interconnect
path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, and design-
dependent. The input and output buffer characteristics are common to all MX devices. Internal routing
delays are device-dependent; actual delays are not determined until after place-and-route of the user's
design is complete. Delay values may then be determined by using the Designer software utility or by
performing simulation with post-layout delays.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are
determined by net property assignment in Microsemi's Designer software prior to placement and routing.
Up to 6% of the nets in a design may be designated as critical.
Long Tracks
Some nets in the design use long tracks, which are special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and sometimes four antifuse connections, which
increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks.
Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add
approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section, shown in Table 1-28 on page 1-40.
Timing Derating
MX devices are manufactured with a CMOS process. Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating
voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating temperature and worst-case processing.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| A42MX24-PQ208A | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-PQ208I | 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| A42MX24-PQ208M | 制造商:Microsemi Corporation 功能描述:FPGA 36K GATES 912 CELLS 0.45UM 3.3V/5V 208PQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208PQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 36K 208-PQFP |
| A42MX24-PQG160 | 功能描述:IC FPGA 176I/O 160PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:24 系列:ECP2 LAB/CLB數(shù):1500 邏輯元件/單元數(shù):12000 RAM 位總計:226304 輸入/輸出數(shù):131 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） |
| A42MX24-PQG160A | 功能描述:IC FPGA MX SGL CHIP 36K 160-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
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