CMOS Output Module Timing5 t
參數(shù)資料
型號: A42MX36-1PQG208I
廠商: Microsemi SoC
文件頁數(shù): 124/142頁
文件大小: 0K
描述: IC FPGA MX SGL CHIP 54K 208-PQFP
標(biāo)準(zhǔn)包裝: 24
系列: MX
RAM 位總計: 2560
輸入/輸出數(shù): 176
門數(shù): 54000
電源電壓: 3 V ~ 3.6 V,4.5 V ~ 5.5 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
40MX and 42MX FPGA Families
1- 78
R e v i sio n 1 1
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
3.5
3.9
4.5
5.2
7.3
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
5.0
5.6
6.3
7.5
10.4
ns
tGHL
G-to-Pad LOW
5.0
5.6
6.3
7.5
10.4
ns
tLSU
I/O Latch Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out
(Pad-to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading,
LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading,
HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
Table 1-38 A42MX36 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, TJ = 70°C)
–3 Speed
–2 Speed
–1 Speed
Std Speed
–F Speed
Parameter / Description
Min. Max. Min. Max. Min. Max. Min. Max. Min.
Max. Units
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input.
External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an
external PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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