參數(shù)資料
型號: A42MX36-FTQ100
廠商: Electronic Theatre Controls, Inc.
英文描述: Quad 2-input positive-NAND gates 14-SSOP 0 to 70
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 50/123頁
文件大?。?/td> 854K
代理商: A42MX36-FTQ100
40MX and 42MX FPGA Families
1-44
v6.0
CMOS Output Module Timing
1
t
DLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5
ns
t
DHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3
ns
t
ENZH
Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3
ns
t
ENZL
Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5
ns
t
ENHZ
Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0
ns
t
ENLZ
Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6
ns
d
TLH
Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07
ns/pF
d
THL
Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04
ns/pF
Table 30
A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
(Worst-Case Commercial Conditions, V
CC
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Units
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to check the hold
time for this macro.
4. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX36-FTQ100A Quad 2-input positive-NAND gates 14-SSOP 0 to 70
A42MX36-FTQ100B Quad 2-input positive-NAND gates 14-SSOP 0 to 70
A42MX36-FTQ100ES Quad 2-input positive-NAND gates 14-SOIC 0 to 70
A42MX36-FTQ100I Quad 2-input positive-NAND gates 14-SOIC 0 to 70
A42MX36-FTQ100M Quad 2-input positive-NAND gates 14-SOIC 0 to 70
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