參數(shù)資料
型號(hào)： A42MX36-FVQ100
廠商： Electronic Theatre Controls, Inc.
英文描述： Quad 2-input positive-NAND gates 14-SOIC 0 to 70
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 68/123頁
文件大?。?/td> 854K
代理商： A42MX36-FVQ100
40MX and 42MX FPGA Families
1-62
v6.0
Table 36
A42MX24 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, V
CCA
= 4.75V, T
J
= 70°C)
‘–3’ Speed
‘–2’Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Logic Module Combinatorial Functions
1
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
t
PD
Internal Array Module Delay
1.2
1.3
1.5
1.8
2.5
ns
t
PDD
Logic Module Predicted Routing Delays
2
Internal Decode Module Delay
1.4
1.6
1.8
2.1
3.0
ns
t
RD1
FO=1 Routing Delay
0.8
0.9
1.0
1.2
1.7
ns
t
RD2
FO=2 Routing Delay
1.0
1.2
1.3
1.5
2.1
ns
t
RD3
FO=3 Routing Delay
1.3
1.4
1.6
1.9
2.6
ns
t
RD4
FO=4 Routing Delay
1.5
1.7
1.9
2.2
3.1
ns
t
RD5
Logic Module Sequential Timing
3, 4
FO=8 Routing Delay
2.4
2.7
3.0
3.6
5.0
ns
t
CO
Flip-Flop Clock-to-Output
1.3
1.4
1.6
1.9
2.7
ns
t
GO
Latch Gate-to-Output
1.2
1.3
1.5
1.8
2.5
ns
t
SUD
Flip-Flop (Latch) Set-Up Time
0.3
0.4
0.4
0.5
0.7
ns
t
HD
Flip-Flop (Latch) Hold Time
0.0
0.0
0.0
0.0
0.0
ns
t
RO
Flip-Flop (Latch) Reset-to-Output
1.4
1.6
1.8
2.1
2.9
ns
t
SUENA
Flip-Flop (Latch) Enable Set-Up
0.4
0.5
0.5
0.6
0.8
ns
t
HENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t
WCLKA
Flip-Flop (Latch) Clock Active
Pulse Width
3.3
3.7
4.2
4.9
6.9
ns
t
WASYN
Flip-Flop (Latch) Asynchronous
Pulse Width
4.4
4.8
5.3
6.5
9.0
ns
Input Module Propagation Delays
t
INPY
Input Data Pad-to-Y
1.0
1.1
1.3
1.5
2.1
ns
t
INGO
Input Latch Gate-to-Output
1.3
1.4
1.6
1.9
2.6
ns
t
INH
Input Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t
INSU
Input Latch Set-Up
0.5
0.5
0.6
0.7
1.0
ns
t
ILA
Latch Active Pulse Width
4.7
5.2
5.9
6.9
9.7
ns
Notes:
1. For dual-module macros, use t
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
RD1
+ t
PDn
, or t
PD1
+ t
RD1
+ t
SUD
, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相關(guān)PDF資料
PDF描述
A42MX36-FVQ100A Quad 2-input positive-NAND gates 14-SOIC 0 to 70
A42MX36-FVQ100B 40MX and 42MX FPGA Families
A42MX36-FVQ100ES Quad 2-input positive-NAND gates 14-PDIP 0 to 70
A42MX36-FVQ100I Quad 2-input positive-NAND gates 14-PDIP 0 to 70
A42MX36-FVQ100M Quad 2-input positive-NAND gates 14-SO 0 to 70
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX36-PQ208 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A42MX36-PQ208A 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
A42MX36-PQ208I 功能描述:IC FPGA MX SGL CHIP 54K 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
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