參數(shù)資料
型號: A5191HRTLG-XTP
廠商: ON Semiconductor
文件頁數(shù): 12/14頁
文件大?。?/td> 0K
描述: MODEM HART SGL CMOS 32LQFP
標準包裝: 1
系列: *
其它名稱: A5191HRTLG-XTPOSDKR
A5191HRT
http://onsemi.com
7
Pin Descriptions
Table 8. PIN DESCRIPTIONS
Symbol
Pin Name
Description
AREF
Analog reference voltage
Receiver Reference Voltage. Normally 1.23 V is selected (in combination with
VDDA = 3.3 V). See Table 2.
CDREF
Carrier detect reference voltage
Carrier Detect Reference voltage. The value should be 85 mV below AREF to set
the carrier detection to a nominal of 100 mVpp.
RESETB
Reset digital logic
When at logic low (VSS) this input holds all the digital logic in reset. During normal
operation RESETB should be at VDD. RESETB should be held low for a minimum
of 10 nS after VDD = 2.5 V as shown in Figure 14.
RTSB
Request to send
Activelow input selects the operation of the modulator. TxA is enabled when this
signal is low. This signal must be held high during powerup.
RxA
Analog receive input
Receive Data Demodulator Input. Accepts a HART 1200 / 2200 Hz FSK modu-
lated waveform input.
RxAFI
Analog receive comparator input
Positive input of the carrier detect comparator and the receiver filter comparator.
TxD
Digital transmit input
Input to the modulator accepts digital data in NRZ form. When TxD is low, the
modulator output frequency is 2200 Hz. When TxD is high, the modulator output
frequency is 1200 Hz.
XIN
Oscillator input
Input to the internal oscillator must be connected to a parallel mode 460.8 kHz
ceramic resonator when using the internal oscillator or grounded when using an
external 460.8 kHz clock signal.
CBIAS
Comparator bias current
Connection to the external bias resistor. RBIAS should be selected such that
AREF / RBIAS = 2.5 mA ± 5 %
CD
Carrier detect output
Output goes high when a valid input is recognized on RxA. If the received signal
is greater than the threshold specified on CDREF for four cycles of the RxA sig-
nal, the valid input is recognized.
RxAF
Analog receive filter output
The output of the three pole high pass receive data filter
RxD
Digital receive output
Signal outputs the digital receive data. When the received signal (RxA) is
1200 Hz, RxD outputs logic high. When the received signal (RxA) is 2200 Hz,
RxD outputs logic low. The HART receive data stream is only active if Carrier
Detect (CD) is high.
TxA
Analog transmit output
Transmit Data Modulator Output. A trapezoidal shaped waveform with a fre-
quency of 1200 Hz or 2200 Hz corresponding to a data value of 1 or 0 respect-
ively applied to TxD. TxA is active when RTSB is low. TxA equals 0.5 V when
RTSB is high.
XOUT
Oscillator output
Output from the internal oscillator must be connected to an external 460.8 kHz
clock signal or to a parallel mode 460.8 kHz ceramic resonator when using the
internal oscillator.
TEST(12:1)
Factory test
Factory test pins; for normal operation, tie these signals as per Tables 6 and 7
VDD
Digital power
Power for the digital modem circuitry
VDDA
Analog supply voltage
Power for the analog modem circuitry
VSS
Ground
Digital ground (and Analog ground in the case of PLCC package)
VSSA
Analog ground
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